83  * 1. All extensions should be separated from other multi-letter extensions
282     "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
399      * with the result for 'map = 1').  in satp_mode_max_from_map()
445             cpu->cfg.satp_mode.supported |= (1 << i);  in set_satp_mode_max_supported()
460         cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE);  in set_satp_mode_default_map()
841     cpuname = g_strsplit(cpu_model, ",", 1);  in riscv_cpu_class_by_name()
977             for (j = vlenb - 1 ; j >= 0; j--) {  in riscv_cpu_dump_state()
1065             env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);  in riscv_cpu_reset_hold()
1095      * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor  in riscv_cpu_reset_hold()
1125     env->load_res = -1;  in riscv_cpu_reset_hold()
1126     set_default_nan_mode(1, &env->fp_status);  in riscv_cpu_reset_hold()
1201             for (int i = 1; i < 16; ++i) {  in riscv_cpu_satp_mode_finalize()
1202                 if ((cpu->cfg.satp_mode.init & (1 << i)) &&  in riscv_cpu_satp_mode_finalize()
1203                     (cpu->cfg.satp_mode.supported & (1 << i))) {  in riscv_cpu_satp_mode_finalize()
1204                     for (int j = i - 1; j >= 0; --j) {  in riscv_cpu_satp_mode_finalize()
1205                         if (cpu->cfg.satp_mode.supported & (1 << j)) {  in riscv_cpu_satp_mode_finalize()
1206                             cpu->cfg.satp_mode.map |= (1 << j);  in riscv_cpu_satp_mode_finalize()
1231         for (int i = satp_mode_map_max - 1; i >= 0; --i) {  in riscv_cpu_satp_mode_finalize()
1232             if (!(cpu->cfg.satp_mode.map & (1 << i)) &&  in riscv_cpu_satp_mode_finalize()
1233                 (cpu->cfg.satp_mode.init & (1 << i)) &&  in riscv_cpu_satp_mode_finalize()
1234                 (cpu->cfg.satp_mode.supported & (1 << i))) {  in riscv_cpu_satp_mode_finalize()
1244     for (int i = satp_mode_map_max - 1; i >= 0; --i) {  in riscv_cpu_satp_mode_finalize()
1245         if (cpu->cfg.satp_mode.supported & (1 << i)) {  in riscv_cpu_satp_mode_finalize()
1246             cpu->cfg.satp_mode.map |= (1 << i);  in riscv_cpu_satp_mode_finalize()
1330     value = satp_map->map & (1 << satp);  in cpu_riscv_get_satp()
1346     satp_map->map = deposit32(satp_map->map, satp, 1, value);  in cpu_riscv_set_satp()
1347     satp_map->init |= 1 << satp;  in cpu_riscv_set_satp()
1390                 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));  in riscv_cpu_set_irq()
1398                 riscv_cpu_update_mip(env, 1 << irq,  in riscv_cpu_set_irq()
1412         irq = irq - IRQ_LOCAL_MAX + 1;  in riscv_cpu_set_irq()
1418         env->hgeip &= ~((target_ulong)1 << irq);  in riscv_cpu_set_irq()
1420             env->hgeip |= (target_ulong)1 << irq;  in riscv_cpu_set_irq()
1564      * Our lowest valid input (RVA) is 1 and  in riscv_validate_misa_info_idx()
1940     int priv_version = -1;  in priv_spec_from_str()
1976     int priv_version = -1;  in prop_priv_spec_set()
2341     invalid_val = 1LL << (mxlen - 1);  in prop_marchid_set()
3104     for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {  in riscv_isa_string()
3122     for (int i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {  in riscv_isa_extensions_list()