Lines Matching +full:0 +full:x14h
45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
249 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
372 * 'map = 0' will make us return (31 - 32), which C will in satp_mode_max_from_map()
374 * return if 'map = 0' (e.g. returning 0 will be ambiguous in satp_mode_max_from_map()
377 * Assert out if map = 0. Callers will have to deal with in satp_mode_max_from_map()
380 g_assert(map > 0); in satp_mode_max_from_map()
419 for (int i = 0; i <= satp_mode; ++i) { in set_satp_mode_max_supported()
731 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); in riscv_cpu_class_by_name()
805 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { in riscv_cpu_dump_state()
807 target_ulong val = 0; in riscv_cpu_dump_state()
808 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
822 for (i = 0; i < 32; i++) { in riscv_cpu_dump_state()
830 target_ulong val = 0; in riscv_cpu_dump_state()
831 RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0); in riscv_cpu_dump_state()
836 for (i = 0; i < 32; i++) { in riscv_cpu_dump_state()
854 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { in riscv_cpu_dump_state()
856 target_ulong val = 0; in riscv_cpu_dump_state()
857 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
870 for (i = 0; i < 32; i++) { in riscv_cpu_dump_state()
873 for (j = vlenb - 1 ; j >= 0; j--) { in riscv_cpu_dump_state()
914 return riscv_cpu_all_pending(env) != 0 || in riscv_cpu_has_work()
963 env->mcause = 0; in riscv_cpu_reset_hold()
966 env->bins = 0; in riscv_cpu_reset_hold()
969 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | in riscv_cpu_reset_hold()
971 MENVCFG_ADUE : 0); in riscv_cpu_reset_hold()
972 env->henvcfg = 0; in riscv_cpu_reset_hold()
975 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { in riscv_cpu_reset_hold()
977 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; in riscv_cpu_reset_hold()
978 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; in riscv_cpu_reset_hold()
979 env->hviprio[i] = 0; in riscv_cpu_reset_hold()
981 i = 0; in riscv_cpu_reset_hold()
1005 env->mseccfg = 0; in riscv_cpu_reset_hold()
1011 env->senvcfg = 0; in riscv_cpu_reset_hold()
1012 env->menvcfg = 0; in riscv_cpu_reset_hold()
1017 /* on reset ssp is set to 0 */ in riscv_cpu_reset_hold()
1018 env->ssp = 0; in riscv_cpu_reset_hold()
1066 if (cpu->cfg.satp_mode.supported == 0) { in riscv_cpu_satp_mode_finalize()
1073 if (cpu->cfg.satp_mode.map == 0) { in riscv_cpu_satp_mode_finalize()
1074 if (cpu->cfg.satp_mode.init == 0) { in riscv_cpu_satp_mode_finalize()
1086 for (int j = i - 1; j >= 0; --j) { in riscv_cpu_satp_mode_finalize()
1113 for (int i = satp_mode_map_max - 1; i >= 0; --i) { in riscv_cpu_satp_mode_finalize()
1126 for (int i = satp_mode_map_max - 1; i >= 0; --i) { in riscv_cpu_satp_mode_finalize()
1443 g_assert(bit != 0); in riscv_validate_misa_info_idx()
1662 if (pmu_num == 0) { in prop_pmu_num_set()
1663 pmu_mask = 0; in prop_pmu_num_set()
1834 if (priv_version < 0) { in prop_priv_spec_set()
1873 if (g_strcmp0(value, VEXT_VER_1_00_0_STR) != 0) { in prop_vext_spec_set()
2094 error_setg(errp, "Unable to change %s mvendorid (0x%x)", in prop_mvendorid_set()
2129 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", in prop_mimpid_set()
2158 uint32_t mxlen = 0; in prop_marchid_set()
2165 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", in prop_marchid_set()
2820 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { in riscv_isa_string()
2825 *p = '\0'; in riscv_isa_string()
2838 for (int i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { in riscv_isa_extensions_list()
2864 int count = 0; in riscv_isa_write_fdt()
2877 for (int i = 0; i < count; i++) { in riscv_isa_write_fdt()