Lines Matching refs:NAME

10 #define TRANS_DFP_T_A_B_Rc(NAME)                             \
11 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
19     gen_helper_##NAME(tcg_env, rt, ra, rb);                  \
26 #define TRANS_DFP_BF_A_B(NAME)                               \
27 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
34     gen_helper_##NAME(cpu_crf[a->bf],                        \
39 #define TRANS_DFP_BF_I_B(NAME)                               \
40 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
46     gen_helper_##NAME(cpu_crf[a->bf],                        \
51 #define TRANS_DFP_BF_A_DCM(NAME)                             \
52 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
58     gen_helper_##NAME(cpu_crf[a->bf],                        \
63 #define TRANS_DFP_T_B_U32_U32_Rc(NAME, U32F1, U32F2)         \
64 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
71     gen_helper_##NAME(tcg_env, rt, rb,                       \
80 #define TRANS_DFP_T_A_B_I32_Rc(NAME, I32FLD)                 \
81 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
89     gen_helper_##NAME(tcg_env, rt, ra, rb,                   \
97 #define TRANS_DFP_T_B_Rc(NAME)                               \
98 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
105     gen_helper_##NAME(tcg_env, rt, rb);                      \
112 #define TRANS_DFP_T_FPR_I32_Rc(NAME, FPRFLD, I32FLD)         \
113 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
120     gen_helper_##NAME(tcg_env, rt, rx,                       \