Lines Matching +full:cpu +full:- +full:2
2 * QEMU OpenRISC CPU
22 #include "qemu/qemu-print.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/translation-block.h"
26 #include "fpu/softfloat-helpers.h"
31 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_set_pc() local
33 cpu->env.pc = value; in openrisc_cpu_set_pc()
34 cpu->env.dflag = 0; in openrisc_cpu_set_pc()
39 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_get_pc() local
41 return cpu->env.pc; in openrisc_cpu_get_pc()
47 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_synchronize_from_tb() local
50 cpu->env.pc = tb->pc; in openrisc_cpu_synchronize_from_tb()
57 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_restore_state_to_opc() local
59 cpu->env.pc = data[0]; in openrisc_restore_state_to_opc()
60 cpu->env.dflag = data[1] & 1; in openrisc_restore_state_to_opc()
61 if (data[1] & 2) { in openrisc_restore_state_to_opc()
62 cpu->env.ppc = cpu->env.pc - 4; in openrisc_restore_state_to_opc()
69 return cs->interrupt_request & (CPU_INTERRUPT_HARD | in openrisc_cpu_has_work()
78 if (env->sr & (ifetch ? SR_IME : SR_DME)) { in openrisc_cpu_mmu_index()
80 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; in openrisc_cpu_mmu_index()
86 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) in openrisc_disas_set_info() argument
88 info->endian = BFD_ENDIAN_BIG; in openrisc_disas_set_info()
89 info->print_insn = print_insn_or1k; in openrisc_disas_set_info()
94 CPUState *cs = CPU(obj); in openrisc_cpu_reset_hold()
95 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_reset_hold() local
98 if (occ->parent_phases.hold) { in openrisc_cpu_reset_hold()
99 occ->parent_phases.hold(obj, type); in openrisc_cpu_reset_hold()
102 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); in openrisc_cpu_reset_hold()
104 cpu->env.pc = 0x100; in openrisc_cpu_reset_hold()
105 cpu->env.sr = SR_FO | SR_SM; in openrisc_cpu_reset_hold()
106 cpu->env.lock_addr = -1; in openrisc_cpu_reset_hold()
107 cs->exception_index = -1; in openrisc_cpu_reset_hold()
108 cpu_set_fpcsr(&cpu->env, 0); in openrisc_cpu_reset_hold()
111 &cpu->env.fp_status); in openrisc_cpu_reset_hold()
116 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); in openrisc_cpu_reset_hold()
119 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); in openrisc_cpu_reset_hold()
122 cpu->env.picmr = 0x00000000; in openrisc_cpu_reset_hold()
123 cpu->env.picsr = 0x00000000; in openrisc_cpu_reset_hold()
125 cpu->env.ttmr = 0x00000000; in openrisc_cpu_reset_hold()
132 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; in openrisc_cpu_set_irq() local
133 CPUState *cs = CPU(cpu); in openrisc_cpu_set_irq()
143 cpu->env.picsr |= irq_bit; in openrisc_cpu_set_irq()
145 cpu->env.picsr &= ~irq_bit; in openrisc_cpu_set_irq()
148 if (cpu->env.picsr & cpu->env.picmr) { in openrisc_cpu_set_irq()
158 CPUState *cs = CPU(dev); in openrisc_cpu_realizefn()
175 occ->parent_realize(dev, errp); in openrisc_cpu_realizefn()
185 /* CPU models */
201 OpenRISCCPU *cpu = OPENRISC_CPU(obj); in or1200_initfn() local
203 cpu->env.vr = 0x13000008; in or1200_initfn()
204 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; in or1200_initfn()
205 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | in or1200_initfn()
209 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) in or1200_initfn()
210 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()
211 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) in or1200_initfn()
212 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()
217 OpenRISCCPU *cpu = OPENRISC_CPU(obj); in openrisc_any_initfn() local
219 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ in openrisc_any_initfn()
220 cpu->env.vr2 = 0; /* No version specific id */ in openrisc_any_initfn()
221 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ in openrisc_any_initfn()
223 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; in openrisc_any_initfn()
224 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | in openrisc_any_initfn()
228 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) in openrisc_any_initfn()
229 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()
230 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) in openrisc_any_initfn()
231 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()
235 #include "hw/core/sysemu-cpu-ops.h"
243 #include "accel/tcg/cpu-ops.h"
267 &occ->parent_realize); in openrisc_cpu_class_init()
269 &occ->parent_phases); in openrisc_cpu_class_init()
271 cc->class_by_name = openrisc_cpu_class_by_name; in openrisc_cpu_class_init()
272 cc->mmu_index = openrisc_cpu_mmu_index; in openrisc_cpu_class_init()
273 cc->dump_state = openrisc_cpu_dump_state; in openrisc_cpu_class_init()
274 cc->set_pc = openrisc_cpu_set_pc; in openrisc_cpu_class_init()
275 cc->get_pc = openrisc_cpu_get_pc; in openrisc_cpu_class_init()
276 cc->gdb_read_register = openrisc_cpu_gdb_read_register; in openrisc_cpu_class_init()
277 cc->gdb_write_register = openrisc_cpu_gdb_write_register; in openrisc_cpu_class_init()
279 dc->vmsd = &vmstate_openrisc_cpu; in openrisc_cpu_class_init()
280 cc->sysemu_ops = &openrisc_sysemu_ops; in openrisc_cpu_class_init()
282 cc->gdb_num_core_regs = 32 + 3; in openrisc_cpu_class_init()
283 cc->disas_set_info = openrisc_disas_set_info; in openrisc_cpu_class_init()
284 cc->tcg_ops = &openrisc_tcg_ops; in openrisc_cpu_class_init()