Lines Matching +full:library +full:- +full:sel
2 * Helpers for emulation of CP0-related MIPS instructions.
4 * Copyright (C) 2004-2005 Jocelyn Mayer
8 * This library is free software; you can redistribute it and/or
13 * This library is distributed in the hope that it will be useful,
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/main-loop.h"
28 #include "qemu/host-utils.h"
29 #include "exec/helper-proto.h"
37 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi()
43 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
49 CPUMIPSState *env = &c->env; in mips_vp_is_wfi()
51 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
57 * Don't set ->halted = 0 directly, let it be done via cpu_has_work in mips_vpe_wake()
74 cs->halted = 1; in mips_vpe_sleep()
80 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
90 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
120 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
122 *tc = env->current_tc; in mips_cpu_map_tc()
127 vpe_idx = tc_idx / cs->nr_threads; in mips_cpu_map_tc()
128 *tc = tc_idx % cs->nr_threads; in mips_cpu_map_tc()
134 return &cpu->env; in mips_cpu_map_tc()
168 tasid = v & cpu->CP0_EntryHi_ASID_mask; in sync_c0_tcstatus()
175 cpu->CP0_Status &= ~mask; in sync_c0_tcstatus()
176 cpu->CP0_Status |= status; in sync_c0_tcstatus()
179 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask; in sync_c0_tcstatus()
180 cpu->CP0_EntryHi |= tasid; in sync_c0_tcstatus()
189 uint32_t asid, v = cpu->CP0_EntryHi; in sync_c0_entryhi()
191 asid = v & cpu->CP0_EntryHi_ASID_mask; in sync_c0_entryhi()
193 if (tc == cpu->current_tc) { in sync_c0_entryhi()
194 tcst = &cpu->active_tc.CP0_TCStatus; in sync_c0_entryhi()
196 tcst = &cpu->tcs[tc].CP0_TCStatus; in sync_c0_entryhi()
199 *tcst &= ~cpu->CP0_EntryHi_ASID_mask; in sync_c0_entryhi()
209 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; in cpu_mips_get_random()
212 return env->tlb->nb_tlb - 1; in cpu_mips_get_random()
222 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; in cpu_mips_get_random()
231 return env->mvp->CP0_MVPControl; in helper_mfc0_mvpcontrol()
236 return env->mvp->CP0_MVPConf0; in helper_mfc0_mvpconf0()
241 return env->mvp->CP0_MVPConf1; in helper_mfc0_mvpconf1()
251 return env->active_tc.CP0_TCStatus; in helper_mfc0_tcstatus()
256 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcstatus()
259 if (other_tc == other->current_tc) { in helper_mftc0_tcstatus()
260 return other->active_tc.CP0_TCStatus; in helper_mftc0_tcstatus()
262 return other->tcs[other_tc].CP0_TCStatus; in helper_mftc0_tcstatus()
268 return env->active_tc.CP0_TCBind; in helper_mfc0_tcbind()
273 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcbind()
276 if (other_tc == other->current_tc) { in helper_mftc0_tcbind()
277 return other->active_tc.CP0_TCBind; in helper_mftc0_tcbind()
279 return other->tcs[other_tc].CP0_TCBind; in helper_mftc0_tcbind()
285 return env->active_tc.PC; in helper_mfc0_tcrestart()
290 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcrestart()
293 if (other_tc == other->current_tc) { in helper_mftc0_tcrestart()
294 return other->active_tc.PC; in helper_mftc0_tcrestart()
296 return other->tcs[other_tc].PC; in helper_mftc0_tcrestart()
302 return env->active_tc.CP0_TCHalt; in helper_mfc0_tchalt()
307 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tchalt()
310 if (other_tc == other->current_tc) { in helper_mftc0_tchalt()
311 return other->active_tc.CP0_TCHalt; in helper_mftc0_tchalt()
313 return other->tcs[other_tc].CP0_TCHalt; in helper_mftc0_tchalt()
319 return env->active_tc.CP0_TCContext; in helper_mfc0_tccontext()
324 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tccontext()
327 if (other_tc == other->current_tc) { in helper_mftc0_tccontext()
328 return other->active_tc.CP0_TCContext; in helper_mftc0_tccontext()
330 return other->tcs[other_tc].CP0_TCContext; in helper_mftc0_tccontext()
336 return env->active_tc.CP0_TCSchedule; in helper_mfc0_tcschedule()
341 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschedule()
344 if (other_tc == other->current_tc) { in helper_mftc0_tcschedule()
345 return other->active_tc.CP0_TCSchedule; in helper_mftc0_tcschedule()
347 return other->tcs[other_tc].CP0_TCSchedule; in helper_mftc0_tcschedule()
353 return env->active_tc.CP0_TCScheFBack; in helper_mfc0_tcschefback()
358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschefback()
361 if (other_tc == other->current_tc) { in helper_mftc0_tcschefback()
362 return other->active_tc.CP0_TCScheFBack; in helper_mftc0_tcschefback()
364 return other->tcs[other_tc].CP0_TCScheFBack; in helper_mftc0_tcschefback()
375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_entryhi()
378 return other->CP0_EntryHi; in helper_mftc0_entryhi()
383 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_cause()
386 return other->CP0_Cause; in helper_mftc0_cause()
391 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_status()
394 return other->CP0_Status; in helper_mftc0_status()
399 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); in helper_mfc0_lladdr()
404 return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; in helper_mfc0_maar()
409 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
412 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchlo() argument
414 return (int32_t)env->CP0_WatchLo[sel]; in helper_mfc0_watchlo()
417 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchhi() argument
419 return (int32_t) env->CP0_WatchHi[sel]; in helper_mfc0_watchhi()
422 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfhc0_watchhi() argument
424 return env->CP0_WatchHi[sel] >> 32; in helper_mfhc0_watchhi()
429 target_ulong t0 = env->CP0_Debug; in helper_mfc0_debug()
430 if (env->hflags & MIPS_HFLAG_DM) { in helper_mfc0_debug()
439 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_debug()
443 if (other_tc == other->current_tc) { in helper_mftc0_debug()
444 tcstatus = other->active_tc.CP0_Debug_tcstatus; in helper_mftc0_debug()
446 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; in helper_mftc0_debug()
450 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | in helper_mftc0_debug()
457 return env->active_tc.PC; in helper_dmfc0_tcrestart()
462 return env->active_tc.CP0_TCHalt; in helper_dmfc0_tchalt()
467 return env->active_tc.CP0_TCContext; in helper_dmfc0_tccontext()
472 return env->active_tc.CP0_TCSchedule; in helper_dmfc0_tcschedule()
477 return env->active_tc.CP0_TCScheFBack; in helper_dmfc0_tcschefback()
482 return env->CP0_LLAddr >> env->CP0_LLAddr_shift; in helper_dmfc0_lladdr()
487 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
490 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchlo() argument
492 return env->CP0_WatchLo[sel]; in helper_dmfc0_watchlo()
495 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchhi() argument
497 return env->CP0_WatchHi[sel]; in helper_dmfc0_watchhi()
504 uint32_t index_p = env->CP0_Index & 0x80000000; in helper_mtc0_index()
506 if (tlb_index < env->tlb->nb_tlb) { in helper_mtc0_index()
507 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_index()
510 env->CP0_Index = index_p | tlb_index; in helper_mtc0_index()
519 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_mvpcontrol()
523 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_mvpcontrol()
526 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol()
530 env->mvp->CP0_MVPControl = newval; in helper_mtc0_mvpcontrol()
540 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mtc0_vpecontrol()
549 env->CP0_VPEControl = newval; in helper_mtc0_vpecontrol()
554 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpecontrol()
561 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mttc0_vpecontrol()
565 other->CP0_VPEControl = newval; in helper_mttc0_vpecontrol()
570 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpecontrol()
573 return other->CP0_VPEControl; in helper_mftc0_vpecontrol()
578 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpeconf0()
581 return other->CP0_VPEConf0; in helper_mftc0_vpeconf0()
589 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_vpeconf0()
590 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { in helper_mtc0_vpeconf0()
595 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf0()
599 env->CP0_VPEConf0 = newval; in helper_mtc0_vpeconf0()
604 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpeconf0()
610 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mttc0_vpeconf0()
613 other->CP0_VPEConf0 = newval; in helper_mttc0_vpeconf0()
621 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) in helper_mtc0_vpeconf1()
624 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf1()
631 env->CP0_VPEConf1 = newval; in helper_mtc0_vpeconf1()
637 env->CP0_YQMask = 0x00000000; in helper_mtc0_yqmask()
642 env->CP0_VPEOpt = arg1 & 0x0000ffff; in helper_mtc0_vpeopt()
645 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
650 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo0()
651 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo0()
652 | (rxi << (CP0EnLo_XI - 30)); in helper_mtc0_entrylo0()
656 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
660 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo0()
661 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo0()
667 uint32_t mask = env->CP0_TCStatus_rw_bitmask; in helper_mtc0_tcstatus()
670 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); in helper_mtc0_tcstatus()
672 env->active_tc.CP0_TCStatus = newval; in helper_mtc0_tcstatus()
673 sync_c0_tcstatus(env, env->current_tc, newval); in helper_mtc0_tcstatus()
678 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcstatus()
681 if (other_tc == other->current_tc) { in helper_mttc0_tcstatus()
682 other->active_tc.CP0_TCStatus = arg1; in helper_mttc0_tcstatus()
684 other->tcs[other_tc].CP0_TCStatus = arg1; in helper_mttc0_tcstatus()
694 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_tcbind()
697 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mtc0_tcbind()
698 env->active_tc.CP0_TCBind = newval; in helper_mtc0_tcbind()
703 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcbind()
708 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mttc0_tcbind()
711 if (other_tc == other->current_tc) { in helper_mttc0_tcbind()
712 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mttc0_tcbind()
713 other->active_tc.CP0_TCBind = newval; in helper_mttc0_tcbind()
715 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); in helper_mttc0_tcbind()
716 other->tcs[other_tc].CP0_TCBind = newval; in helper_mttc0_tcbind()
722 env->active_tc.PC = arg1; in helper_mtc0_tcrestart()
723 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mtc0_tcrestart()
724 env->CP0_LLAddr = 0; in helper_mtc0_tcrestart()
725 env->lladdr = 0; in helper_mtc0_tcrestart()
731 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcrestart()
734 if (other_tc == other->current_tc) { in helper_mttc0_tcrestart()
735 other->active_tc.PC = arg1; in helper_mttc0_tcrestart()
736 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mttc0_tcrestart()
737 other->CP0_LLAddr = 0; in helper_mttc0_tcrestart()
738 other->lladdr = 0; in helper_mttc0_tcrestart()
741 other->tcs[other_tc].PC = arg1; in helper_mttc0_tcrestart()
742 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mttc0_tcrestart()
743 other->CP0_LLAddr = 0; in helper_mttc0_tcrestart()
744 other->lladdr = 0; in helper_mttc0_tcrestart()
753 env->active_tc.CP0_TCHalt = arg1 & 0x1; in helper_mtc0_tchalt()
756 if (env->active_tc.CP0_TCHalt & 1) { in helper_mtc0_tchalt()
757 mips_tc_sleep(cpu, env->current_tc); in helper_mtc0_tchalt()
759 mips_tc_wake(cpu, env->current_tc); in helper_mtc0_tchalt()
765 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tchalt()
771 if (other_tc == other->current_tc) { in helper_mttc0_tchalt()
772 other->active_tc.CP0_TCHalt = arg1; in helper_mttc0_tchalt()
774 other->tcs[other_tc].CP0_TCHalt = arg1; in helper_mttc0_tchalt()
786 env->active_tc.CP0_TCContext = arg1; in helper_mtc0_tccontext()
791 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tccontext()
794 if (other_tc == other->current_tc) { in helper_mttc0_tccontext()
795 other->active_tc.CP0_TCContext = arg1; in helper_mttc0_tccontext()
797 other->tcs[other_tc].CP0_TCContext = arg1; in helper_mttc0_tccontext()
803 env->active_tc.CP0_TCSchedule = arg1; in helper_mtc0_tcschedule()
808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschedule()
811 if (other_tc == other->current_tc) { in helper_mttc0_tcschedule()
812 other->active_tc.CP0_TCSchedule = arg1; in helper_mttc0_tcschedule()
814 other->tcs[other_tc].CP0_TCSchedule = arg1; in helper_mttc0_tcschedule()
820 env->active_tc.CP0_TCScheFBack = arg1; in helper_mtc0_tcschefback()
825 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschefback()
828 if (other_tc == other->current_tc) { in helper_mttc0_tcschefback()
829 other->active_tc.CP0_TCScheFBack = arg1; in helper_mttc0_tcschefback()
831 other->tcs[other_tc].CP0_TCScheFBack = arg1; in helper_mttc0_tcschefback()
838 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo1()
839 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo1()
840 | (rxi << (CP0EnLo_XI - 30)); in helper_mtc0_entrylo1()
846 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo1()
847 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo1()
853 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); in helper_mtc0_context()
859 old = env->CP0_MemoryMapID; in helper_mtc0_memorymapid()
860 env->CP0_MemoryMapID = (int32_t) arg1; in helper_mtc0_memorymapid()
862 if (old != env->CP0_MemoryMapID) { in helper_mtc0_memorymapid()
884 env->CP0_PageMask = compute_pagemask(arg1); in helper_mtc0_pagemask()
891 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) | in helper_mtc0_pagegrain()
892 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask); in helper_mtc0_pagegrain()
901 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; in helper_mtc0_segctl0()
909 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; in helper_mtc0_segctl1()
917 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; in helper_mtc0_segctl2()
925 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; in helper_mtc0_pwfield()
928 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
945 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
948 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
950 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) | in helper_mtc0_pwfield()
955 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; in helper_mtc0_pwfield()
958 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
972 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
975 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
977 env->CP0_PWField = (env->CP0_PWField & ~0x3F) | in helper_mtc0_pwfield()
986 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL; in helper_mtc0_pwsize()
988 env->CP0_PWSize = arg1 & 0x3FFFFFFF; in helper_mtc0_pwsize()
994 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_wired()
995 if (arg1 < env->tlb->nb_tlb) { in helper_mtc0_wired()
996 env->CP0_Wired = arg1; in helper_mtc0_wired()
999 env->CP0_Wired = arg1 % env->tlb->nb_tlb; in helper_mtc0_wired()
1007 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); in helper_mtc0_pwctl()
1009 env->CP0_PWCtl = (arg1 & 0x800000FF); in helper_mtc0_pwctl()
1015 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; in helper_mtc0_srsconf0()
1020 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; in helper_mtc0_srsconf1()
1025 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; in helper_mtc0_srsconf2()
1030 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; in helper_mtc0_srsconf3()
1035 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()
1042 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && in helper_mtc0_hwrena()
1043 (env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_hwrena()
1046 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_hwrena()
1049 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { in helper_mtc0_hwrena()
1053 env->hflags |= MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1055 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1059 env->CP0_HWREna = arg1 & mask; in helper_mtc0_hwrena()
1070 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; in helper_mtc0_entryhi()
1071 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { in helper_mtc0_entryhi()
1077 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_entryhi()
1079 int config0_at = extract32(env->CP0_Config0, 13, 2); in helper_mtc0_entryhi()
1080 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; in helper_mtc0_entryhi()
1087 mask &= env->SEGMask; in helper_mtc0_entryhi()
1089 old = env->CP0_EntryHi; in helper_mtc0_entryhi()
1091 env->CP0_EntryHi = val; in helper_mtc0_entryhi()
1093 sync_c0_entryhi(env, env->current_tc); in helper_mtc0_entryhi()
1096 if ((old & env->CP0_EntryHi_ASID_mask) != in helper_mtc0_entryhi()
1097 (val & env->CP0_EntryHi_ASID_mask)) { in helper_mtc0_entryhi()
1104 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_entryhi()
1107 other->CP0_EntryHi = arg1; in helper_mttc0_entryhi()
1120 old = env->CP0_Status; in helper_mtc0_status()
1122 val = env->CP0_Status; in helper_mtc0_status()
1126 old, old & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1127 val, val & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1128 env->CP0_Cause); in helper_mtc0_status()
1151 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_status()
1152 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; in helper_mttc0_status()
1155 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); in helper_mttc0_status()
1161 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); in helper_mtc0_intctl()
1167 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); in helper_mtc0_srsctl()
1177 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_cause()
1185 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_epc()
1188 return other->CP0_EPC; in helper_mftc0_epc()
1193 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_ebase()
1196 return other->CP0_EBase; in helper_mftc0_ebase()
1201 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mtc0_ebase()
1202 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mtc0_ebase()
1205 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask); in helper_mtc0_ebase()
1210 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_ebase()
1212 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mttc0_ebase()
1213 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mttc0_ebase()
1216 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask); in helper_mttc0_ebase()
1221 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_configx()
1225 case 0: return other->CP0_Config0; in helper_mftc0_configx()
1226 case 1: return other->CP0_Config1; in helper_mftc0_configx()
1227 case 2: return other->CP0_Config2; in helper_mftc0_configx()
1228 case 3: return other->CP0_Config3; in helper_mftc0_configx()
1230 case 6: return other->CP0_Config6; in helper_mftc0_configx()
1231 case 7: return other->CP0_Config7; in helper_mftc0_configx()
1240 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); in helper_mtc0_config0()
1246 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); in helper_mtc0_config2()
1251 if (env->insn_flags & ASE_MICROMIPS) { in helper_mtc0_config3()
1252 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | in helper_mtc0_config3()
1259 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1260 (arg1 & env->CP0_Config4_rw_bitmask); in helper_mtc0_config4()
1265 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1266 (arg1 & env->CP0_Config5_rw_bitmask); in helper_mtc0_config5()
1267 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1268 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in helper_mtc0_config5()
1274 target_long mask = env->CP0_LLAddr_rw_bitmask; in helper_mtc0_lladdr()
1275 arg1 = arg1 << env->CP0_LLAddr_shift; in helper_mtc0_lladdr()
1276 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask); in helper_mtc0_lladdr()
1280 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1284 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1289 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1291 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); in helper_mthc0_maar()
1302 env->CP0_MAARI = MIPS_MAAR_MAX - 1; in helper_mtc0_maari()
1304 env->CP0_MAARI = index; in helper_mtc0_maari()
1312 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchlo() argument
1318 env->CP0_WatchLo[sel] = (arg1 & ~0x7); in helper_mtc0_watchlo()
1321 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchhi() argument
1323 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); in helper_mtc0_watchhi()
1324 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ in helper_mtc0_watchhi()
1325 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
1328 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); in helper_mtc0_watchhi()
1329 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); in helper_mtc0_watchhi()
1332 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mthc0_watchhi() argument
1334 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | in helper_mthc0_watchhi()
1335 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); in helper_mthc0_watchhi()
1340 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; in helper_mtc0_xcontext()
1341 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); in helper_mtc0_xcontext()
1346 env->CP0_Framemask = arg1; /* XXX */ in helper_mtc0_framemask()
1351 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); in helper_mtc0_debug()
1353 env->hflags |= MIPS_HFLAG_DM; in helper_mtc0_debug()
1355 env->hflags &= ~MIPS_HFLAG_DM; in helper_mtc0_debug()
1361 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_debug()
1366 if (other_tc == other->current_tc) { in helper_mttc0_debug()
1367 other->active_tc.CP0_Debug_tcstatus = val; in helper_mttc0_debug()
1369 other->tcs[other_tc].CP0_Debug_tcstatus = val; in helper_mttc0_debug()
1371 other->CP0_Debug = (other->CP0_Debug & in helper_mttc0_debug()
1378 env->CP0_Performance0 = arg1 & 0x000007ff; in helper_mtc0_performance0()
1385 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; in helper_mtc0_errctl()
1387 env->CP0_ErrCtl = wst | spr | itc; in helper_mtc0_errctl()
1390 env->hflags |= MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1392 env->hflags &= ~MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1398 if (env->hflags & MIPS_HFLAG_ITC_CACHE) { in helper_mtc0_taglo()
1402 * Tag will take care of the read-only bits. in helper_mtc0_taglo()
1404 env->CP0_TagLo = arg1; in helper_mtc0_taglo()
1406 env->CP0_TagLo = arg1 & 0xFFFFFCF6; in helper_mtc0_taglo()
1412 env->CP0_DataLo = arg1; /* XXX */ in helper_mtc0_datalo()
1417 env->CP0_TagHi = arg1; /* XXX */ in helper_mtc0_taghi()
1422 env->CP0_DataHi = arg1; /* XXX */ in helper_mtc0_datahi()
1426 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) in helper_mftgpr() argument
1428 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftgpr()
1431 if (other_tc == other->current_tc) { in helper_mftgpr()
1432 return other->active_tc.gpr[sel]; in helper_mftgpr()
1434 return other->tcs[other_tc].gpr[sel]; in helper_mftgpr()
1438 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) in helper_mftlo() argument
1440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftlo()
1443 if (other_tc == other->current_tc) { in helper_mftlo()
1444 return other->active_tc.LO[sel]; in helper_mftlo()
1446 return other->tcs[other_tc].LO[sel]; in helper_mftlo()
1450 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) in helper_mfthi() argument
1452 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mfthi()
1455 if (other_tc == other->current_tc) { in helper_mfthi()
1456 return other->active_tc.HI[sel]; in helper_mfthi()
1458 return other->tcs[other_tc].HI[sel]; in helper_mfthi()
1462 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) in helper_mftacx() argument
1464 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftacx()
1467 if (other_tc == other->current_tc) { in helper_mftacx()
1468 return other->active_tc.ACX[sel]; in helper_mftacx()
1470 return other->tcs[other_tc].ACX[sel]; in helper_mftacx()
1476 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftdsp()
1479 if (other_tc == other->current_tc) { in helper_mftdsp()
1480 return other->active_tc.DSPControl; in helper_mftdsp()
1482 return other->tcs[other_tc].DSPControl; in helper_mftdsp()
1486 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttgpr() argument
1488 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttgpr()
1491 if (other_tc == other->current_tc) { in helper_mttgpr()
1492 other->active_tc.gpr[sel] = arg1; in helper_mttgpr()
1494 other->tcs[other_tc].gpr[sel] = arg1; in helper_mttgpr()
1498 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttlo() argument
1500 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttlo()
1503 if (other_tc == other->current_tc) { in helper_mttlo()
1504 other->active_tc.LO[sel] = arg1; in helper_mttlo()
1506 other->tcs[other_tc].LO[sel] = arg1; in helper_mttlo()
1510 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtthi() argument
1512 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mtthi()
1515 if (other_tc == other->current_tc) { in helper_mtthi()
1516 other->active_tc.HI[sel] = arg1; in helper_mtthi()
1518 other->tcs[other_tc].HI[sel] = arg1; in helper_mtthi()
1522 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttacx() argument
1524 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttacx()
1527 if (other_tc == other->current_tc) { in helper_mttacx()
1528 other->active_tc.ACX[sel] = arg1; in helper_mttacx()
1530 other->tcs[other_tc].ACX[sel] = arg1; in helper_mttacx()
1536 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttdsp()
1539 if (other_tc == other->current_tc) { in helper_mttdsp()
1540 other->active_tc.DSPControl = arg1; in helper_mttdsp()
1542 other->tcs[other_tc].DSPControl = arg1; in helper_mttdsp()
1562 target_ulong prev = env->mvp->CP0_MVPControl; in helper_dvpe()
1567 if (&other_cpu->env != env) { in helper_dvpe()
1568 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); in helper_dvpe()
1578 target_ulong prev = env->mvp->CP0_MVPControl; in helper_evpe()
1583 if (&other_cpu->env != env in helper_evpe()
1587 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); in helper_evpe()
1594 /* R6 Multi-threading */
1598 target_ulong prev = env->CP0_VPControl; in helper_dvp()
1600 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { in helper_dvp()
1604 if (&other_cpu->env != env) { in helper_dvp()
1608 env->CP0_VPControl |= (1 << CP0VPCtl_DIS); in helper_dvp()
1616 target_ulong prev = env->CP0_VPControl; in helper_evp()
1618 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { in helper_evp()
1621 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) { in helper_evp()
1629 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS); in helper_evp()