Lines Matching +full:0 +full:x7c000000
42 #define MB_CPU_IRQ 0
47 #define SR_PC 0
52 #define SR_BTR 0xb
53 #define SR_EDR 0xd
56 #define MSR_BE (1<<0) /* 0x001 */
57 #define MSR_IE (1<<1) /* 0x002 */
58 #define MSR_C (1<<2) /* 0x004 */
59 #define MSR_BIP (1<<3) /* 0x008 */
60 #define MSR_FSL (1<<4) /* 0x010 */
61 #define MSR_ICE (1<<5) /* 0x020 */
62 #define MSR_DZ (1<<6) /* 0x040 */
63 #define MSR_DCE (1<<7) /* 0x080 */
64 #define MSR_EE (1<<8) /* 0x100 */
65 #define MSR_EIP (1<<9) /* 0x200 */
66 #define MSR_PVR (1<<10) /* 0x400 */
87 #define ESR_ESS_MASK (0x7f << 5)
89 #define ESR_EC_FSL 0
109 #define FSR_DO (1<<0) /* Denormalized operand error */
113 #define PVR0_PVR_FULL_MASK 0x80000000
114 #define PVR0_USE_BARREL_MASK 0x40000000
115 #define PVR0_USE_DIV_MASK 0x20000000
116 #define PVR0_USE_HW_MUL_MASK 0x10000000
117 #define PVR0_USE_FPU_MASK 0x08000000
118 #define PVR0_USE_EXC_MASK 0x04000000
119 #define PVR0_USE_ICACHE_MASK 0x02000000
120 #define PVR0_USE_DCACHE_MASK 0x01000000
121 #define PVR0_USE_MMU_MASK 0x00800000
122 #define PVR0_USE_BTC 0x00400000
123 #define PVR0_ENDI_MASK 0x00200000
124 #define PVR0_FAULT 0x00100000
125 #define PVR0_VERSION_MASK 0x0000FF00
126 #define PVR0_USER1_MASK 0x000000FF
127 #define PVR0_SPROT_MASK 0x00000001
132 #define PVR1_USER2_MASK 0xFFFFFFFF
135 #define PVR2_D_OPB_MASK 0x80000000
136 #define PVR2_D_LMB_MASK 0x40000000
137 #define PVR2_I_OPB_MASK 0x20000000
138 #define PVR2_I_LMB_MASK 0x10000000
139 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
140 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
141 #define PVR2_D_PLB_MASK 0x02000000 /* new */
142 #define PVR2_I_PLB_MASK 0x01000000 /* new */
143 #define PVR2_INTERCONNECT 0x00800000 /* new */
144 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
145 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
146 #define PVR2_USE_MSR_INSTR 0x00020000
147 #define PVR2_USE_PCMP_INSTR 0x00010000
148 #define PVR2_AREA_OPTIMISED 0x00008000
149 #define PVR2_USE_BARREL_MASK 0x00004000
150 #define PVR2_USE_DIV_MASK 0x00002000
151 #define PVR2_USE_HW_MUL_MASK 0x00001000
152 #define PVR2_USE_FPU_MASK 0x00000800
153 #define PVR2_USE_MUL64_MASK 0x00000400
154 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
155 #define PVR2_USE_IPLBEXC 0x00000100
156 #define PVR2_USE_DPLBEXC 0x00000080
157 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
158 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
159 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
160 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
161 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
162 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
163 #define PVR2_FPU_EXC_MASK 0x00000001
166 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
167 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
168 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
169 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
170 #define PVR3_FSL_LINKS_MASK 0x00000380
173 #define PVR4_USE_ICACHE_MASK 0x80000000
174 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
175 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
176 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
177 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
178 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
181 #define PVR5_USE_DCACHE_MASK 0x80000000
182 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
183 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
184 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
185 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
186 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
187 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
190 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
193 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
196 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
199 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
202 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
206 #define PVR11_USE_MMU 0xC0000000
207 #define PVR11_MMU_ITLB_SIZE 0x38000000
208 #define PVR11_MMU_DTLB_SIZE 0x07000000
209 #define PVR11_MMU_TLB_ACCESS 0x00C00000
210 #define PVR11_MMU_ZONES 0x003E0000
212 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
214 #define C_PVR_NONE 0
226 #define CC_EQ 0
228 #define STREAM_EXCEPTION (1 << 0)
237 #define USE_NON_SECURE_M_AXI_DP_MASK 0x1
238 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2
239 #define USE_NON_SECURE_M_AXI_DC_MASK 0x4
240 #define USE_NON_SECURE_M_AXI_IC_MASK 0x8
250 uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
261 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
266 #define IMM_FLAG (1 << 0)
407 #define MMU_NOMMU_IDX 0
429 *cs_base = (*flags & IMM_FLAG ? env->imm : 0); in cpu_get_tb_cpu_state()