Lines Matching +full:7 +full:c80
55 #define REG(insn, pos) (((insn) >> (pos)) & 7)
59 #define QREG_SP get_areg(s, 7)
667 switch ((ext >> pos) & 7) { in ext_opsize()
733 if (reg0 == 7 && opsize == OS_BYTE && in gen_lea_mode()
749 case 7: /* Other */ in gen_lea_mode()
820 if (reg0 == 7 && opsize == OS_BYTE && in gen_ea_mode()
861 case 7: /* Other */ in gen_ea_mode()
1108 case 7: /* Other */ in gen_ea_mode_fp()
1202 case 7: /* EQ */ in gen_cc_cond()
1263 case 7: /* EQ (Z) */ in gen_cc_cond()
1316 case 7: /* EQ (Z) */ in gen_cc_cond()
1879 tcg_gen_andi_i32(src2, DREG(insn, 9), 7); in DISAS_INSN()
1933 return cpu_aregs[reg & 7]; in mreg()
2118 bitnum &= 7; in DISAS_INSN()
2218 op = (insn >> 9) & 7; in DISAS_INSN()
2505 op = (insn >> 6) & 7; in DISAS_INSN()
2514 dest_ea = ((insn >> 9) & 7) | (op << 3); in DISAS_INSN()
2655 if ((insn & 7) == 0 && semihosting_test(s)) { in DISAS_INSN()
2682 op = (insn >> 6) & 7; in DISAS_INSN()
2822 if ((insn & 7) != 7) { in gen_link()
2946 imm = (insn >> 9) & 7; in DISAS_INSN()
3142 val = (insn >> 9) & 7; in DISAS_INSN()
3343 int count = (insn >> 9) & 7; in shift_im()
3728 tmp = (insn >> 9) & 7; in DISAS_INSN()
3753 tmp = (insn >> 9) & 7; in DISAS_INSN()
3777 tmp = (insn >> 9) & 7; in DISAS_INSN()
3838 tcg_gen_andi_i32(t1, src, 7); in DISAS_INSN()
4254 switch ((insn >> 7) & 3) { in DISAS_INSN()
4465 REG(insn, 0) == 7 && opsize == OS_BYTE in DISAS_INSN()
4782 int mask = (ext >> 10) & 7; in gen_op_fmove_fcr()
4811 case 7: /* Immediate */ in gen_op_fmove_fcr()
4948 switch ((ext >> 13) & 7) { in DISAS_INSN()
4957 cpu_dest = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
4963 cpu_src = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
4976 case 7: in DISAS_INSN()
4997 cpu_dest = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
5232 case 7: /* Ordered !A */ in gen_fcc_cond()
5446 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); in DISAS_INSN()
5585 switch ((insn >> 3) & 7) { in DISAS_INSN()
5864 INSN(sats, 4c80, fff8, CF_ISA_B); in register_m68k_insns()