Lines Matching +full:0 +full:- +full:mon
4 * Copyright (c) 2003-2004 Fabrice Bellard
28 #include "monitor/hmp-target.h"
32 #include "qapi/qapi-commands-misc-target.h"
33 #include "qapi/qapi-commands-misc.h"
39 if (env->cr[4] & CR4_LA57_MASK) { in addr_canonical()
41 addr |= (hwaddr)-(1LL << 57); in addr_canonical()
45 addr |= (hwaddr)-(1LL << 48); in addr_canonical()
52 static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, in print_pte() argument
57 monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx in print_pte()
61 pte & PG_NX_MASK ? 'X' : '-', in print_pte()
62 pte & PG_GLOBAL_MASK ? 'G' : '-', in print_pte()
63 pte & PG_PSE_MASK ? 'P' : '-', in print_pte()
64 pte & PG_DIRTY_MASK ? 'D' : '-', in print_pte()
65 pte & PG_ACCESSED_MASK ? 'A' : '-', in print_pte()
66 pte & PG_PCD_MASK ? 'C' : '-', in print_pte()
67 pte & PG_PWT_MASK ? 'T' : '-', in print_pte()
68 pte & PG_USER_MASK ? 'U' : '-', in print_pte()
69 pte & PG_RW_MASK ? 'W' : '-'); in print_pte()
72 static void tlb_info_32(Monitor *mon, CPUArchState *env) in tlb_info_32() argument
77 pgd = env->cr[3] & ~0xfff; in tlb_info_32()
78 for(l1 = 0; l1 < 1024; l1++) { in tlb_info_32()
82 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { in tlb_info_32()
84 print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); in tlb_info_32()
86 for(l2 = 0; l2 < 1024; l2++) { in tlb_info_32()
87 cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); in tlb_info_32()
90 print_pte(mon, env, (l1 << 22) + (l2 << 12), in tlb_info_32()
92 ~0xfff); in tlb_info_32()
100 static void tlb_info_pae32(Monitor *mon, CPUArchState *env) in tlb_info_pae32() argument
106 pdp_addr = env->cr[3] & ~0x1f; in tlb_info_pae32()
107 for (l1 = 0; l1 < 4; l1++) { in tlb_info_pae32()
111 pd_addr = pdpe & 0x3fffffffff000ULL; in tlb_info_pae32()
112 for (l2 = 0; l2 < 512; l2++) { in tlb_info_pae32()
118 print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, in tlb_info_pae32()
119 ~((hwaddr)(1 << 20) - 1)); in tlb_info_pae32()
121 pt_addr = pde & 0x3fffffffff000ULL; in tlb_info_pae32()
122 for (l3 = 0; l3 < 512; l3++) { in tlb_info_pae32()
126 print_pte(mon, env, (l1 << 30) + (l2 << 21) in tlb_info_pae32()
129 ~(hwaddr)0xfff); in tlb_info_pae32()
140 static void tlb_info_la48(Monitor *mon, CPUArchState *env, in tlb_info_la48() argument
147 for (l1 = 0; l1 < 512; l1++) { in tlb_info_la48()
154 pdp_addr = pml4e & 0x3fffffffff000ULL; in tlb_info_la48()
155 for (l2 = 0; l2 < 512; l2++) { in tlb_info_la48()
164 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), in tlb_info_la48()
165 pdpe, 0x3ffffc0000000ULL); in tlb_info_la48()
169 pd_addr = pdpe & 0x3fffffffff000ULL; in tlb_info_la48()
170 for (l3 = 0; l3 < 512; l3++) { in tlb_info_la48()
179 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + in tlb_info_la48()
180 (l3 << 21), pde, 0x3ffffffe00000ULL); in tlb_info_la48()
184 pt_addr = pde & 0x3fffffffff000ULL; in tlb_info_la48()
185 for (l4 = 0; l4 < 512; l4++) { in tlb_info_la48()
191 print_pte(mon, env, (l0 << 48) + (l1 << 39) + in tlb_info_la48()
193 pte & ~PG_PSE_MASK, 0x3fffffffff000ULL); in tlb_info_la48()
201 static void tlb_info_la57(Monitor *mon, CPUArchState *env) in tlb_info_la57() argument
207 pml5_addr = env->cr[3] & 0x3fffffffff000ULL; in tlb_info_la57()
208 for (l0 = 0; l0 < 512; l0++) { in tlb_info_la57()
212 tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); in tlb_info_la57()
218 void hmp_info_tlb(Monitor *mon, const QDict *qdict) in hmp_info_tlb() argument
222 env = mon_get_cpu_env(mon); in hmp_info_tlb()
224 monitor_printf(mon, "No CPU available\n"); in hmp_info_tlb()
228 if (!(env->cr[0] & CR0_PG_MASK)) { in hmp_info_tlb()
229 monitor_printf(mon, "PG disabled\n"); in hmp_info_tlb()
232 if (env->cr[4] & CR4_PAE_MASK) { in hmp_info_tlb()
234 if (env->hflags & HF_LMA_MASK) { in hmp_info_tlb()
235 if (env->cr[4] & CR4_LA57_MASK) { in hmp_info_tlb()
236 tlb_info_la57(mon, env); in hmp_info_tlb()
238 tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL); in hmp_info_tlb()
243 tlb_info_pae32(mon, env); in hmp_info_tlb()
246 tlb_info_32(mon, env); in hmp_info_tlb()
250 static void mem_print(Monitor *mon, CPUArchState *env, in mem_print() argument
257 if (*pstart != -1) { in mem_print()
258 monitor_printf(mon, HWADDR_FMT_plx "-" HWADDR_FMT_plx " " in mem_print()
262 addr_canonical(env, end - *pstart), in mem_print()
263 prot1 & PG_USER_MASK ? 'u' : '-', in mem_print()
265 prot1 & PG_RW_MASK ? 'w' : '-'); in mem_print()
267 if (prot != 0) in mem_print()
270 *pstart = -1; in mem_print()
275 static void mem_info_32(Monitor *mon, CPUArchState *env) in mem_info_32() argument
282 pgd = env->cr[3] & ~0xfff; in mem_info_32()
283 last_prot = 0; in mem_info_32()
284 start = -1; in mem_info_32()
285 for(l1 = 0; l1 < 1024; l1++) { in mem_info_32()
290 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { in mem_info_32()
292 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_32()
294 for(l2 = 0; l2 < 1024; l2++) { in mem_info_32()
295 cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); in mem_info_32()
302 prot = 0; in mem_info_32()
304 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_32()
308 prot = 0; in mem_info_32()
309 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_32()
313 mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0); in mem_info_32()
316 static void mem_info_pae32(Monitor *mon, CPUArchState *env) in mem_info_pae32() argument
324 pdp_addr = env->cr[3] & ~0x1f; in mem_info_pae32()
325 last_prot = 0; in mem_info_pae32()
326 start = -1; in mem_info_pae32()
327 for (l1 = 0; l1 < 4; l1++) { in mem_info_pae32()
332 pd_addr = pdpe & 0x3fffffffff000ULL; in mem_info_pae32()
333 for (l2 = 0; l2 < 512; l2++) { in mem_info_pae32()
341 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_pae32()
343 pt_addr = pde & 0x3fffffffff000ULL; in mem_info_pae32()
344 for (l3 = 0; l3 < 512; l3++) { in mem_info_pae32()
352 prot = 0; in mem_info_pae32()
354 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_pae32()
358 prot = 0; in mem_info_pae32()
359 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_pae32()
363 prot = 0; in mem_info_pae32()
364 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_pae32()
368 mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0); in mem_info_pae32()
373 static void mem_info_la48(Monitor *mon, CPUArchState *env) in mem_info_la48() argument
380 pml4_addr = env->cr[3] & 0x3fffffffff000ULL; in mem_info_la48()
381 last_prot = 0; in mem_info_la48()
382 start = -1; in mem_info_la48()
383 for (l1 = 0; l1 < 512; l1++) { in mem_info_la48()
388 pdp_addr = pml4e & 0x3fffffffff000ULL; in mem_info_la48()
389 for (l2 = 0; l2 < 512; l2++) { in mem_info_la48()
398 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la48()
400 pd_addr = pdpe & 0x3fffffffff000ULL; in mem_info_la48()
401 for (l3 = 0; l3 < 512; l3++) { in mem_info_la48()
410 mem_print(mon, env, &start, in mem_info_la48()
413 pt_addr = pde & 0x3fffffffff000ULL; in mem_info_la48()
414 for (l4 = 0; l4 < 512; l4++) { in mem_info_la48()
426 prot = 0; in mem_info_la48()
428 mem_print(mon, env, &start, in mem_info_la48()
433 prot = 0; in mem_info_la48()
434 mem_print(mon, env, &start, in mem_info_la48()
440 prot = 0; in mem_info_la48()
441 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la48()
445 prot = 0; in mem_info_la48()
446 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la48()
450 mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0); in mem_info_la48()
453 static void mem_info_la57(Monitor *mon, CPUArchState *env) in mem_info_la57() argument
460 pml5_addr = env->cr[3] & 0x3fffffffff000ULL; in mem_info_la57()
461 last_prot = 0; in mem_info_la57()
462 start = -1; in mem_info_la57()
463 for (l0 = 0; l0 < 512; l0++) { in mem_info_la57()
468 prot = 0; in mem_info_la57()
469 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
473 pml4_addr = pml5e & 0x3fffffffff000ULL; in mem_info_la57()
474 for (l1 = 0; l1 < 512; l1++) { in mem_info_la57()
479 prot = 0; in mem_info_la57()
480 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
484 pdp_addr = pml4e & 0x3fffffffff000ULL; in mem_info_la57()
485 for (l2 = 0; l2 < 512; l2++) { in mem_info_la57()
490 prot = 0; in mem_info_la57()
491 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
499 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
503 pd_addr = pdpe & 0x3fffffffff000ULL; in mem_info_la57()
504 for (l3 = 0; l3 < 512; l3++) { in mem_info_la57()
509 prot = 0; in mem_info_la57()
510 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
518 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
522 pt_addr = pde & 0x3fffffffff000ULL; in mem_info_la57()
523 for (l4 = 0; l4 < 512; l4++) { in mem_info_la57()
533 prot = 0; in mem_info_la57()
535 mem_print(mon, env, &start, &last_prot, end, prot); in mem_info_la57()
542 mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 57, 0); in mem_info_la57()
546 void hmp_info_mem(Monitor *mon, const QDict *qdict) in hmp_info_mem() argument
550 env = mon_get_cpu_env(mon); in hmp_info_mem()
552 monitor_printf(mon, "No CPU available\n"); in hmp_info_mem()
556 if (!(env->cr[0] & CR0_PG_MASK)) { in hmp_info_mem()
557 monitor_printf(mon, "PG disabled\n"); in hmp_info_mem()
560 if (env->cr[4] & CR4_PAE_MASK) { in hmp_info_mem()
562 if (env->hflags & HF_LMA_MASK) { in hmp_info_mem()
563 if (env->cr[4] & CR4_LA57_MASK) { in hmp_info_mem()
564 mem_info_la57(mon, env); in hmp_info_mem()
566 mem_info_la48(mon, env); in hmp_info_mem()
571 mem_info_pae32(mon, env); in hmp_info_mem()
574 mem_info_32(mon, env); in hmp_info_mem()
578 void hmp_mce(Monitor *mon, const QDict *qdict) in hmp_mce() argument
596 cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc, in hmp_mce()
601 static target_long monitor_get_pc(Monitor *mon, const struct MonitorDef *md, in monitor_get_pc() argument
604 CPUArchState *env = mon_get_cpu_env(mon); in monitor_get_pc()
605 return env->eip + env->segs[R_CS].base; in monitor_get_pc()
614 { "eax", offsetof(CPUX86State, regs[0]) },
640 { "pc", 0, monitor_get_pc, },