Lines Matching +full:0 +full:x259
51 R_EAX = 0,
68 R_AL = 0,
79 R_ES = 0,
108 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
118 #define CC_C 0x0001
119 #define CC_P 0x0004
120 #define CC_A 0x0010
121 #define CC_Z 0x0040
122 #define CC_S 0x0080
123 #define CC_O 0x0800
129 #define TF_MASK 0x00000100
130 #define IF_MASK 0x00000200
131 #define DF_MASK 0x00000400
132 #define IOPL_MASK 0x00003000
133 #define NT_MASK 0x00004000
134 #define RF_MASK 0x00010000
135 #define VM_MASK 0x00020000
136 #define AC_MASK 0x00040000
137 #define VIF_MASK 0x00080000
138 #define VIP_MASK 0x00100000
139 #define ID_MASK 0x00200000
146 #define HF_CPL_SHIFT 0
152 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
206 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
213 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
226 #define CR0_PE_SHIFT 0
229 #define CR0_PE_MASK (1U << 0)
241 #define CR4_VME_MASK (1U << 0)
269 #define CR4_FRED_MASK 0
285 #define DR6_FIXED_1 0xffff0ff0
290 #define DR7_FIXED_1 0x00000400
291 #define DR7_GLOBAL_BP_MASK 0xaa
292 #define DR7_LOCAL_BP_MASK 0x55
294 #define DR7_TYPE_BP_INST 0x0
295 #define DR7_TYPE_DATA_WR 0x1
296 #define DR7_TYPE_IO_RW 0x2
297 #define DR7_TYPE_DATA_RW 0x3
299 #define DR_RESERVED_MASK 0xffffffff00000000ULL
301 #define PG_PRESENT_BIT 0
324 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
325 #define PG_HI_USER_MASK 0x7ff0000000000000LL
331 #define PG_ERROR_P_MASK 0x01
333 #define PG_ERROR_U_MASK 0x04
334 #define PG_ERROR_RSVD_MASK 0x08
335 #define PG_ERROR_I_D_MASK 0x10
336 #define PG_ERROR_PK_MASK 0x20
338 #define PG_MODE_PAE (1 << 0)
343 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
359 #define MCG_CAP_BANKS_MASK 0xff
361 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
366 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
381 #define MCM_ADDR_SEGOFF 0 /* segment offset */
387 #define MSR_IA32_TSC 0x10
388 #define MSR_IA32_APICBASE 0x1b
392 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
397 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
398 #define MSR_TSC_ADJUST 0x0000003b
399 #define MSR_IA32_SPEC_CTRL 0x48
400 #define MSR_VIRT_SSBD 0xc001011f
401 #define MSR_IA32_PRED_CMD 0x49
402 #define MSR_IA32_UCODE_REV 0x8b
403 #define MSR_IA32_CORE_CAPABILITY 0xcf
405 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
408 #define MSR_IA32_PERF_CAPABILITIES 0x345
409 #define PERF_CAP_LBR_FMT 0x3f
411 #define MSR_IA32_TSX_CTRL 0x122
412 #define MSR_IA32_TSCDEADLINE 0x6e0
413 #define MSR_IA32_PKRS 0x6e1
414 #define MSR_RAPL_POWER_UNIT 0x00000606
415 #define MSR_PKG_POWER_LIMIT 0x00000610
416 #define MSR_PKG_ENERGY_STATUS 0x00000611
417 #define MSR_PKG_POWER_INFO 0x00000614
418 #define MSR_ARCH_LBR_CTL 0x000014ce
419 #define MSR_ARCH_LBR_DEPTH 0x000014cf
420 #define MSR_ARCH_LBR_FROM_0 0x00001500
421 #define MSR_ARCH_LBR_TO_0 0x00001600
422 #define MSR_ARCH_LBR_INFO_0 0x00001200
424 #define FEATURE_CONTROL_LOCKED (1<<0)
431 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
432 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
433 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
434 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
436 #define MSR_P6_PERFCTR0 0xc1
438 #define MSR_IA32_SMBASE 0x9e
439 #define MSR_SMI_COUNT 0x34
440 #define MSR_CORE_THREAD_COUNT 0x35
441 #define MSR_MTRRcap 0xfe
446 #define MSR_IA32_SYSENTER_CS 0x174
447 #define MSR_IA32_SYSENTER_ESP 0x175
448 #define MSR_IA32_SYSENTER_EIP 0x176
450 #define MSR_MCG_CAP 0x179
451 #define MSR_MCG_STATUS 0x17a
452 #define MSR_MCG_CTL 0x17b
453 #define MSR_MCG_EXT_CTL 0x4d0
455 #define MSR_P6_EVNTSEL0 0x186
457 #define MSR_IA32_PERF_STATUS 0x198
459 #define MSR_IA32_MISC_ENABLE 0x1a0
464 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
465 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
467 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
469 #define MSR_MTRRfix64K_00000 0x250
470 #define MSR_MTRRfix16K_80000 0x258
471 #define MSR_MTRRfix16K_A0000 0x259
472 #define MSR_MTRRfix4K_C0000 0x268
473 #define MSR_MTRRfix4K_C8000 0x269
474 #define MSR_MTRRfix4K_D0000 0x26a
475 #define MSR_MTRRfix4K_D8000 0x26b
476 #define MSR_MTRRfix4K_E0000 0x26c
477 #define MSR_MTRRfix4K_E8000 0x26d
478 #define MSR_MTRRfix4K_F0000 0x26e
479 #define MSR_MTRRfix4K_F8000 0x26f
481 #define MSR_PAT 0x277
483 #define MSR_MTRRdefType 0x2ff
485 #define MSR_CORE_PERF_FIXED_CTR0 0x309
486 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
487 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
488 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
489 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
490 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
491 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
493 #define MSR_MC0_CTL 0x400
494 #define MSR_MC0_STATUS 0x401
495 #define MSR_MC0_ADDR 0x402
496 #define MSR_MC0_MISC 0x403
498 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
499 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
500 #define MSR_IA32_RTIT_CTL 0x570
501 #define MSR_IA32_RTIT_STATUS 0x571
502 #define MSR_IA32_RTIT_CR3_MATCH 0x572
503 #define MSR_IA32_RTIT_ADDR0_A 0x580
504 #define MSR_IA32_RTIT_ADDR0_B 0x581
505 #define MSR_IA32_RTIT_ADDR1_A 0x582
506 #define MSR_IA32_RTIT_ADDR1_B 0x583
507 #define MSR_IA32_RTIT_ADDR2_A 0x584
508 #define MSR_IA32_RTIT_ADDR2_B 0x585
509 #define MSR_IA32_RTIT_ADDR3_A 0x586
510 #define MSR_IA32_RTIT_ADDR3_B 0x587
513 #define MSR_EFER 0xc0000080
515 #define MSR_EFER_SCE (1 << 0)
527 #define MSR_STAR 0xc0000081
528 #define MSR_LSTAR 0xc0000082
529 #define MSR_CSTAR 0xc0000083
530 #define MSR_FMASK 0xc0000084
531 #define MSR_FSBASE 0xc0000100
532 #define MSR_GSBASE 0xc0000101
533 #define MSR_KERNELGSBASE 0xc0000102
534 #define MSR_TSC_AUX 0xc0000103
535 #define MSR_AMD64_TSC_RATIO 0xc0000104
537 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
539 #define MSR_K7_HWCR 0xc0010015
541 #define MSR_VM_HSAVE_PA 0xc0010117
543 #define MSR_IA32_XFD 0x000001c4
544 #define MSR_IA32_XFD_ERR 0x000001c5
547 #define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */
548 #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
549 #define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */
550 #define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */
551 #define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */
552 #define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in r…
553 #define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in r…
554 #define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in r…
555 #define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack lev…
557 #define MSR_IA32_BNDCFGS 0x00000d90
558 #define MSR_IA32_XSS 0x00000da0
559 #define MSR_IA32_UMWAIT_CONTROL 0xe1
561 #define MSR_IA32_VMX_BASIC 0x00000480
562 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
563 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
564 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
565 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
566 #define MSR_IA32_VMX_MISC 0x00000485
567 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
568 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
569 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
570 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
571 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
572 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
573 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
574 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
575 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
576 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
577 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
578 #define MSR_IA32_VMX_VMFUNC 0x00000491
580 #define MSR_APIC_START 0x00000800
581 #define MSR_APIC_END 0x000008ff
583 #define XSTATE_FP_BIT 0
630 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
631 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
632 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
646 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
648 FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
649 FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
663 FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
664 FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
665 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
666 FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
667 FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
670 FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
678 #define CPUID_FP87 (1U << 0)
709 #define CPUID_EXT_SSE3 (1U << 0)
740 #define CPUID_EXT2_FPU (1U << 0)
780 #define CPUID_EXT3_LAHF_LM (1U << 0)
803 #define CPUID_SVM_NPT (1U << 0)
820 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
955 #define CPUID_7_1_EAX_SHA512 (1U << 0)
999 #define CPUID_7_2_EDX_PSFD (1U << 0)
1029 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
1055 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
1076 #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0)
1101 #define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0)
1103 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
1110 /* CPUID[0x80000007].EDX flags: */
1136 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1137 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1138 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1141 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
1142 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
1143 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
1146 #define CPUID_VENDOR_ZHAOXIN1_1 0x746E6543 /* "Cent" */
1147 #define CPUID_VENDOR_ZHAOXIN1_2 0x48727561 /* "aurH" */
1148 #define CPUID_VENDOR_ZHAOXIN1_3 0x736C7561 /* "auls" */
1150 #define CPUID_VENDOR_ZHAOXIN2_1 0x68532020 /* " Sh" */
1151 #define CPUID_VENDOR_ZHAOXIN2_2 0x68676E61 /* "angh" */
1152 #define CPUID_VENDOR_ZHAOXIN2_3 0x20206961 /* "ai " */
1176 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1178 /* CPUID[0xB].ECX level types */
1179 #define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
1183 /* COUID[0x1F].ECX level types */
1191 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1212 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1213 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1214 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1221 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1226 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1230 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1248 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1252 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1253 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1254 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1255 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1256 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1257 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1258 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1259 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1260 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1261 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1262 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1263 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1264 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1265 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1266 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1267 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1268 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1269 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1270 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1271 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1272 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1274 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1275 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1276 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1277 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1278 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1279 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1280 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1281 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1282 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1283 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1284 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1285 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1286 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1287 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1288 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1289 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1290 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1291 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1292 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1293 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1294 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000
1296 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1297 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1298 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1299 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1300 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1302 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1303 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1304 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1305 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1306 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1307 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1308 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1309 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1310 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1311 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1312 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1313 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1314 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1315 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1317 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1318 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1319 #define VMX_VM_ENTRY_SMM 0x00000400
1320 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1321 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1322 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1323 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1324 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1325 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1326 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1327 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1330 #define HYPERV_FEAT_RELAXED 0
1353 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1356 #define EXCP00_DIVZ 0
1375 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1376 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1377 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1401 CC_OP_EFLAGS = 0, /* all cc are explicitly computed, CC_SRC = flags */
1408 CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */
1458 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1463 CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
1617 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1620 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1722 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1723 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1724 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1725 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1726 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1727 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1728 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1729 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1730 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1731 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1768 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1770 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1774 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1784 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1789 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1801 * CPUID[0x8000001D].EAX[bits 25:14].
1832 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1862 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
2008 }; /* break/watchpoints for dr[0..3] */
2189 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2246 * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2438 } else if (!(env->cr[0] & CR0_PE_MASK) || in cpu_x86_load_seg_cache()
2450 env->segs[R_SS].base) != 0) << in cpu_x86_load_seg_cache()
2464 env->eip = 0; in cpu_x86_load_seg_cache_sipi()
2469 cs->halted = 0; in cpu_x86_load_seg_cache_sipi()
2567 #define MMU_KSMAP64_IDX 0
2621 *cs_base = 0; in cpu_get_tb_cpu_state()
2651 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); in cpu_get_mem_attrs()
2754 #define CPU_VERSION_LEGACY 0
2768 #define APIC_DEFAULT_ADDRESS 0xfee00000
2769 #define APIC_SPACE_SIZE 0x100000