Lines Matching +full:0 +full:x8000000a
68 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
70 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
72 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
74 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
76 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
78 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
80 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
82 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
84 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
87 * so descriptors 0x22, 0x23 are not included
89 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
92 * so descriptors 0x25, 0x20 are not included
94 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
96 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
98 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
100 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
102 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
104 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
106 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
108 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
110 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
112 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
114 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
115 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
117 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
119 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
121 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
123 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
125 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
127 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
129 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
131 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
133 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
136 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
138 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
140 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
142 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
144 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
146 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
148 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
150 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
152 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
156 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
164 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
166 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
168 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
170 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
172 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
174 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
180 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
182 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
184 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
192 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
202 assert(cache->size > 0); in cpuid2_cache_descriptor()
203 assert(cache->level > 0); in cpuid2_cache_descriptor()
204 assert(cache->line_size > 0); in cpuid2_cache_descriptor()
205 assert(cache->associativity > 0); in cpuid2_cache_descriptor()
206 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { in cpuid2_cache_descriptor()
230 #define CACHE_NO_INVD_SHARING (1 << 0)
238 0 /* Invalid value */)
243 uint32_t num_ids = 0; in max_thread_ids_for_cache()
284 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | in encode_cache_cpuid4()
288 assert(cache->line_size > 0); in encode_cache_cpuid4()
289 assert(cache->partitions > 0); in encode_cache_cpuid4()
290 assert(cache->associativity > 0); in encode_cache_cpuid4()
297 assert(cache->sets > 0); in encode_cache_cpuid4()
300 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid4()
301 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid4()
302 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid4()
324 return 0; in num_threads_by_topo_level()
332 return 0; in apicid_offset_by_topo_level()
344 return 0; in apicid_offset_by_topo_level()
364 return 0; in cpuid1f_topo_type()
380 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). in encode_topo_cpuid1f()
384 for (int i = 0; i <= count; i++) { in encode_topo_cpuid1f()
390 * CPUID[0x1f] doesn't explicitly encode the package level, in encode_topo_cpuid1f()
391 * and it just encodes the invalid level (all fields are 0) in encode_topo_cpuid1f()
392 * into the last subleaf of 0x1f. in encode_topo_cpuid1f()
403 num_threads_next_level = 0; in encode_topo_cpuid1f()
404 offset_next_level = 0; in encode_topo_cpuid1f()
417 *ebx = num_threads_next_level & 0xffff; in encode_topo_cpuid1f()
418 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); in encode_topo_cpuid1f()
421 assert(!(*eax & ~0x1f)); in encode_topo_cpuid1f()
424 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
427 assert(cache->size % 1024 == 0); in encode_cache_cpuid80000005()
428 assert(cache->lines_per_tag > 0); in encode_cache_cpuid80000005()
429 assert(cache->associativity > 0); in encode_cache_cpuid80000005()
430 assert(cache->line_size > 0); in encode_cache_cpuid80000005()
435 #define ASSOC_FULL 0xFF
437 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
439 a == 2 ? 0x2 : \
440 a == 4 ? 0x4 : \
441 a == 8 ? 0x6 : \
442 a == 16 ? 0x8 : \
443 a == 32 ? 0xA : \
444 a == 48 ? 0xB : \
445 a == 64 ? 0xC : \
446 a == 96 ? 0xD : \
447 a == 128 ? 0xE : \
448 a == ASSOC_FULL ? 0xF : \
449 0 /* invalid value */)
452 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
459 assert(l2->size % 1024 == 0); in encode_cache_cpuid80000006()
460 assert(l2->associativity > 0); in encode_cache_cpuid80000006()
461 assert(l2->lines_per_tag > 0); in encode_cache_cpuid80000006()
462 assert(l2->line_size > 0); in encode_cache_cpuid80000006()
468 assert(l3->size % (512 * 1024) == 0); in encode_cache_cpuid80000006()
469 assert(l3->associativity > 0); in encode_cache_cpuid80000006()
470 assert(l3->lines_per_tag > 0); in encode_cache_cpuid80000006()
471 assert(l3->line_size > 0); in encode_cache_cpuid80000006()
476 *edx = 0; in encode_cache_cpuid80000006()
490 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); in encode_cache_cpuid8000001d()
493 assert(cache->line_size > 0); in encode_cache_cpuid8000001d()
494 assert(cache->partitions > 0); in encode_cache_cpuid8000001d()
495 assert(cache->associativity > 0); in encode_cache_cpuid8000001d()
502 assert(cache->sets > 0); in encode_cache_cpuid8000001d()
505 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid8000001d()
506 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid8000001d()
507 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid8000001d()
525 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; in encode_topo_cpuid8000001e()
530 * 7:0 CoreId: core ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
535 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); in encode_topo_cpuid8000001e()
540 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; in encode_topo_cpuid8000001e()
546 * 0h 1 node per processor. in encode_topo_cpuid8000001e()
548 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
558 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); in encode_topo_cpuid8000001e()
560 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; in encode_topo_cpuid8000001e()
563 *edx = 0; in encode_topo_cpuid8000001e()
586 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
615 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
655 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
696 #define L2_DTLB_2M_ASSOC 0 /* disabled */
697 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
701 #define L2_ITLB_2M_ASSOC 0 /* disabled */
702 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
706 /* CPUID Leaf 0x14 constants: */
707 #define INTEL_PT_MAX_SUBLEAF 0x1
716 #define INTEL_PT_MINIMAL_EBX 0xf
726 #define INTEL_PT_MINIMAL_ECX 0x7
729 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
730 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
731 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
732 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
733 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
735 /* CPUID Leaf 0x1D constants: */
736 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
737 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
738 #define INTEL_AMX_BYTES_PER_TILE 0x400
739 #define INTEL_AMX_BYTES_PER_ROW 0x40
740 #define INTEL_AMX_TILE_MAX_NAMES 0x8
741 #define INTEL_AMX_TILE_MAX_ROWS 0x10
743 /* CPUID Leaf 0x1E constants: */
744 #define INTEL_AMX_TMUL_MAX_K 0x10
745 #define INTEL_AMX_TMUL_MAX_N 0x40
751 for (i = 0; i < 4; i++) { in x86_cpu_vendor_words2str()
756 dst[CPUID_VENDOR_SZ] = '\0'; in x86_cpu_vendor_words2str()
790 #define CPUID_EXT_KERNEL_FEATURES 0
809 #define TCG_EXT2_X86_64_FEATURES 0
830 #define CPUID_EXT2_KERNEL_FEATURES 0
842 #define CPUID_EXT3_KERNEL_FEATURES 0
849 #define TCG_EXT4_FEATURES 0
854 #define CPUID_SVM_KERNEL_FEATURES 0
859 #define TCG_KVM_FEATURES 0
864 #define CPUID_7_0_EBX_KERNEL_FEATURES 0
879 #define TCG_7_0_ECX_RDPID 0
890 #define CPUID_7_0_EDX_KERNEL_FEATURES 0
896 #define TCG_7_1_EDX_FEATURES 0
897 #define TCG_7_2_EDX_FEATURES 0
898 #define TCG_APM_FEATURES 0
903 #define TCG_14_0_ECX_FEATURES 0
904 #define TCG_SGX_12_0_EAX_FEATURES 0
905 #define TCG_SGX_12_0_EBX_FEATURES 0
906 #define TCG_SGX_12_1_EAX_FEATURES 0
907 #define TCG_24_0_EBX_FEATURES 0
915 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
970 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
985 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
1006 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
1042 .no_autoenable_flags = ~0U,
1056 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1073 .needs_ecx = true, .ecx = 0,
1092 .needs_ecx = true, .ecx = 0,
1111 .needs_ecx = true, .ecx = 0,
1181 .eax = 0x24,
1182 .needs_ecx = true, .ecx = 0,
1199 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1215 .cpuid = { .eax = 0x80000007, .reg = R_EBX, },
1216 .tcg_features = 0,
1217 .unmigratable_flags = 0,
1231 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1233 .unmigratable_flags = 0,
1247 .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
1248 .tcg_features = 0,
1249 .unmigratable_flags = 0,
1253 .cpuid = { .eax = 0x80000021, .reg = R_EBX, },
1254 .tcg_features = 0,
1255 .unmigratable_flags = 0,
1269 .cpuid = { .eax = 0x80000022, .reg = R_EAX, },
1270 .tcg_features = 0,
1271 .unmigratable_flags = 0,
1286 .eax = 0xd,
1305 .eax = 0xD,
1314 .eax = 0xD,
1338 .eax = 0xD,
1339 .needs_ecx = true, .ecx = 0,
1353 .eax = 0xD,
1354 .needs_ecx = true, .ecx = 0,
1357 .tcg_features = 0U,
1381 .tcg_features = ~0U,
1567 [0] = "vmx-eptp-switching",
1587 .eax = 0x14,
1588 .needs_ecx = true, .ecx = 0,
1607 .eax = 0x12,
1608 .needs_ecx = true, .ecx = 0,
1627 .eax = 0x12,
1628 .needs_ecx = true, .ecx = 0,
1647 .eax = 0x12,
1667 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1671 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1675 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1679 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1683 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1687 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1691 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1695 .to = { FEAT_VMX_MISC, ~0ull },
1699 .to = { FEAT_VMX_BASIC, ~0ull },
1707 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1735 .to = { FEAT_14_0_ECX, ~0ull },
1743 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1751 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1755 .to = { FEAT_VMX_VMFUNC, ~0ull },
1759 .to = { FEAT_SVM, ~0ull },
1783 .to = { FEAT_SGX_12_0_EAX, ~0ull },
1787 .to = { FEAT_SGX_12_0_EBX, ~0ull },
1791 .to = { FEAT_SGX_12_1_EAX, ~0ull },
1807 .to = { FEAT_24_0_EBX, ~0ull },
1869 .offset = 0 /*supervisor mode component, offset = 0 */,
1883 uint64_t ret = x86_ext_save_areas[0].size; in xsave_area_size()
1885 uint32_t offset = 0; in xsave_area_size()
1932 uint64_t r = 0; in x86_cpu_get_migratable_flags()
1935 for (i = 0; i < 64; i++) { in x86_cpu_get_migratable_flags()
1961 : "=a"(vec[0]), "=b"(vec[1]), in host_cpuid()
1963 : "0"(function), "c"(count) : "cc"); in host_cpuid()
1967 "mov %%eax, 0(%2) \n\t" in host_cpuid()
1979 *eax = vec[0]; in host_cpuid()
2035 * List is terminated by item with version == 0.
2060 assert(version > 0); in x86_cpu_versioned_model_name()
2465 * Inject event with insn length=0 (Skylake and newer)
2485 .level = 0xd,
2500 .xlevel = 0x8000000A,
2532 .xlevel = 0x8000001A,
2574 .xlevel = 0x80000008,
2579 .level = 0xd,
2600 0,
2615 .xlevel = 0x80000008,
2629 .xlevel = 0x80000004,
2645 0,
2659 .xlevel = 0x80000008,
2692 .xlevel = 0x80000008,
2701 .stepping = 0,
2704 .xlevel = 0,
2716 .xlevel = 0,
2728 .xlevel = 0,
2740 .xlevel = 0,
2755 .xlevel = 0x80000008,
2780 .xlevel = 0x80000008,
2820 .xlevel = 0x80000008,
2864 .xlevel = 0x80000008,
2927 .xlevel = 0x80000008,
3008 .xlevel = 0x80000008,
3027 .level = 0xd,
3094 .xlevel = 0x80000008,
3113 .level = 0xd,
3186 .xlevel = 0x80000008,
3205 .level = 0xd,
3283 .xlevel = 0x80000008,
3334 .level = 0xd,
3414 .xlevel = 0x80000008,
3458 .level = 0xd,
3538 .xlevel = 0x80000008,
3577 .level = 0xd,
3664 .xlevel = 0x80000008,
3714 .level = 0xd,
3804 .xlevel = 0x80000008,
3848 .level = 0xd,
3946 .xlevel = 0x80000008,
3963 .level = 0xd,
3967 .stepping = 0,
4057 .xlevel = 0x80000008,
4130 .level = 0x20,
4250 .xlevel = 0x80000008,
4279 .level = 0x20,
4283 .stepping = 0,
4406 .xlevel = 0x80000008,
4432 .level = 0x23,
4436 .stepping = 0,
4549 .xlevel = 0x80000008,
4641 .xlevel = 0x80000008,
4774 .xlevel = 0x80000008,
4809 .level = 0xd,
4813 .stepping = 0,
4846 .xlevel = 0x80000008,
4866 .xlevel = 0x80000008,
4888 .xlevel = 0x80000008,
4913 .xlevel = 0x80000008,
4918 .level = 0xd,
4945 .xlevel = 0x8000001A,
4950 .level = 0xd,
4954 .stepping = 0,
4977 .xlevel = 0x8000001A,
4982 .level = 0xd,
5020 .xlevel = 0x8000001E,
5062 .level = 0xd,
5065 .model = 0,
5102 .xlevel = 0x8000001E,
5119 .level = 0xd,
5123 .stepping = 0,
5163 .xlevel = 0x8000001E,
5200 .level = 0xd,
5249 .xlevel = 0x8000001E,
5275 .level = 0xd,
5279 .stepping = 0,
5341 .xlevel = 0x80000022,
5365 int v = 0; in x86_cpu_model_last_version()
5479 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_have_filtered_features()
5504 for (i = 0; i < 64; ++i) { in mark_unavailable_features()
5524 value = (env->cpuid_version >> 8) & 0xf; in x86_cpuid_version_get_family()
5525 if (value == 0xf) { in x86_cpuid_version_get_family()
5526 value += (env->cpuid_version >> 20) & 0xff; in x86_cpuid_version_get_family()
5537 const uint64_t max = 0xff + 0xf; in x86_cpuid_version_set_family()
5549 env->cpuid_version &= ~0xff00f00; in x86_cpuid_version_set_family()
5550 if (value > 0x0f) { in x86_cpuid_version_set_family()
5551 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); in x86_cpuid_version_set_family()
5565 value = (env->cpuid_version >> 4) & 0xf; in x86_cpuid_version_get_model()
5566 value |= ((env->cpuid_version >> 16) & 0xf) << 4; in x86_cpuid_version_get_model()
5576 const uint64_t max = 0xff; in x86_cpuid_version_set_model()
5588 env->cpuid_version &= ~0xf00f0; in x86_cpuid_version_set_model()
5589 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); in x86_cpuid_version_set_model()
5600 value = env->cpuid_version & 0xf; in x86_cpuid_version_get_stepping()
5610 const uint64_t max = 0xf; in x86_cpuid_version_set_stepping()
5622 env->cpuid_version &= ~0xf; in x86_cpuid_version_set_stepping()
5623 env->cpuid_version |= value & 0xf; in x86_cpuid_version_set_stepping()
5651 env->cpuid_vendor1 = 0; in x86_cpuid_set_vendor()
5652 env->cpuid_vendor2 = 0; in x86_cpuid_set_vendor()
5653 env->cpuid_vendor3 = 0; in x86_cpuid_set_vendor()
5654 for (i = 0; i < 4; i++) { in x86_cpuid_set_vendor()
5669 for (i = 0; i < 48; i++) { in x86_cpuid_get_model_id()
5672 value[48] = '\0'; in x86_cpuid_get_model_id()
5687 memset(env->cpuid_model, 0, 48); in x86_cpuid_set_model_id()
5688 for (i = 0; i < 48; i++) { in x86_cpuid_set_model_id()
5690 c = '\0'; in x86_cpuid_set_model_id()
5718 if (value < 0 || value > max) { in x86_cpuid_set_tsc_freq()
5738 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_get_feature_words()
5837 if (featurestr[0] == '+') { in x86_cpu_parse_featurestr()
5841 } else if (featurestr[0] == '-') { in x86_cpu_parse_featurestr()
5849 *eq++ = 0; in x86_cpu_parse_featurestr()
5877 if (ret < 0 || tsc_freq > INT64_MAX) { in x86_cpu_parse_featurestr()
5908 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_list_feature_names()
5911 for (i = 0; i < 64; i++) { in x86_cpu_list_feature_names()
5934 size_t len = 0; in listflags()
5941 len = 0; in listflags()
5943 qemu_printf("%s%s", len == 0 ? " " : " ", name); in listflags()
5991 if (version <= 0) { in x86_cpu_class_get_alias_of()
6041 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { in x86_cpu_list()
6043 for (j = 0; j < 64; j++) { in x86_cpu_list()
6139 uint64_t r = 0; in x86_cpu_get_supported_feature_word()
6140 uint64_t unavail = 0; in x86_cpu_get_supported_feature_word()
6156 return 0; in x86_cpu_get_supported_feature_word()
6164 return ~0; in x86_cpu_get_supported_feature_word()
6184 unavail = ~0; in x86_cpu_get_supported_feature_word()
6229 *eax = 0; in x86_cpu_get_supported_cpuid()
6230 *ebx = 0; in x86_cpu_get_supported_cpuid()
6231 *ecx = 0; in x86_cpu_get_supported_cpuid()
6232 *edx = 0; in x86_cpu_get_supported_cpuid()
6246 host_cpuid(0, 0, &level, &unused, &unused, &unused); in x86_cpu_get_cache_cpuid()
6248 case 0x80000005: in x86_cpu_get_cache_cpuid()
6249 case 0x80000006: in x86_cpu_get_cache_cpuid()
6250 case 0x8000001d: in x86_cpu_get_cache_cpuid()
6251 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); in x86_cpu_get_cache_cpuid()
6258 *eax = 0; in x86_cpu_get_cache_cpuid()
6259 *ebx = 0; in x86_cpu_get_cache_cpuid()
6260 *ecx = 0; in x86_cpu_get_cache_cpuid()
6261 *edx = 0; in x86_cpu_get_cache_cpuid()
6367 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_load_model()
6400 memset(&env->user_features, 0, sizeof(env->user_features)); in x86_cpu_load_model()
6515 if (index >= 0xC0000000) { in cpu_x86_cpuid()
6517 } else if (index >= 0x80000000) { in cpu_x86_cpuid()
6519 } else if (index >= 0x40000000) { in cpu_x86_cpuid()
6520 limit = 0x40000001; in cpu_x86_cpuid()
6534 case 0: in cpu_x86_cpuid()
6560 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); in cpu_x86_cpuid()
6563 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6567 *ebx = 0; in cpu_x86_cpuid()
6569 *ecx = 0; in cpu_x86_cpuid()
6586 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); in cpu_x86_cpuid()
6588 *eax &= ~0xFC000000; in cpu_x86_cpuid()
6591 *eax &= ~0x3FFC000; in cpu_x86_cpuid()
6599 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6601 *eax = 0; in cpu_x86_cpuid()
6604 case 0: /* L1 dcache info */ in cpu_x86_cpuid()
6634 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6649 *ebx = 0; in cpu_x86_cpuid()
6650 *ecx = 0; in cpu_x86_cpuid()
6651 *edx = 0; in cpu_x86_cpuid()
6655 if (count == 0) { in cpu_x86_cpuid()
6667 *ebx = 0; in cpu_x86_cpuid()
6668 *ecx = 0; in cpu_x86_cpuid()
6671 *eax = 0; in cpu_x86_cpuid()
6672 *ebx = 0; in cpu_x86_cpuid()
6673 *ecx = 0; in cpu_x86_cpuid()
6675 *eax = 0; in cpu_x86_cpuid()
6676 *ebx = 0; in cpu_x86_cpuid()
6677 *ecx = 0; in cpu_x86_cpuid()
6678 *edx = 0; in cpu_x86_cpuid()
6683 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ in cpu_x86_cpuid()
6684 *ebx = 0; in cpu_x86_cpuid()
6685 *ecx = 0; in cpu_x86_cpuid()
6686 *edx = 0; in cpu_x86_cpuid()
6688 case 0xA: in cpu_x86_cpuid()
6691 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); in cpu_x86_cpuid()
6693 *eax = 0; in cpu_x86_cpuid()
6694 *ebx = 0; in cpu_x86_cpuid()
6695 *ecx = 0; in cpu_x86_cpuid()
6696 *edx = 0; in cpu_x86_cpuid()
6699 case 0xB: in cpu_x86_cpuid()
6702 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6706 *ecx = count & 0xff; in cpu_x86_cpuid()
6710 case 0: in cpu_x86_cpuid()
6721 *eax = 0; in cpu_x86_cpuid()
6722 *ebx = 0; in cpu_x86_cpuid()
6726 assert(!(*eax & ~0x1f)); in cpu_x86_cpuid()
6727 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ in cpu_x86_cpuid()
6729 case 0x1C: in cpu_x86_cpuid()
6731 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); in cpu_x86_cpuid()
6732 *edx = 0; in cpu_x86_cpuid()
6735 case 0x1F: in cpu_x86_cpuid()
6738 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6744 case 0xD: { in cpu_x86_cpuid()
6746 *eax = 0; in cpu_x86_cpuid()
6747 *ebx = 0; in cpu_x86_cpuid()
6748 *ecx = 0; in cpu_x86_cpuid()
6749 *edx = 0; in cpu_x86_cpuid()
6754 if (count == 0) { in cpu_x86_cpuid()
6759 * The initial value of xcr0 and ebx == 0, On host without kvm in cpu_x86_cpuid()
6760 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 in cpu_x86_cpuid()
6780 } else if (count == 0xf && cpu->enable_pmu in cpu_x86_cpuid()
6782 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); in cpu_x86_cpuid()
6793 *ebx = 0; in cpu_x86_cpuid()
6799 case 0x12: in cpu_x86_cpuid()
6803 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6808 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve in cpu_x86_cpuid()
6817 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
6821 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; in cpu_x86_cpuid()
6823 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); in cpu_x86_cpuid()
6829 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware in cpu_x86_cpuid()
6834 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); in cpu_x86_cpuid()
6836 if (count == 0) { in cpu_x86_cpuid()
6841 *ebx &= 0; /* ebx reserve */ in cpu_x86_cpuid()
6856 case 0x14: { in cpu_x86_cpuid()
6858 *eax = 0; in cpu_x86_cpuid()
6859 *ebx = 0; in cpu_x86_cpuid()
6860 *ecx = 0; in cpu_x86_cpuid()
6861 *edx = 0; in cpu_x86_cpuid()
6871 if (count == 0) { in cpu_x86_cpuid()
6884 case 0x1D: { in cpu_x86_cpuid()
6886 *eax = 0; in cpu_x86_cpuid()
6887 *ebx = 0; in cpu_x86_cpuid()
6888 *ecx = 0; in cpu_x86_cpuid()
6889 *edx = 0; in cpu_x86_cpuid()
6894 if (count == 0) { in cpu_x86_cpuid()
6905 case 0x1E: { in cpu_x86_cpuid()
6907 *eax = 0; in cpu_x86_cpuid()
6908 *ebx = 0; in cpu_x86_cpuid()
6909 *ecx = 0; in cpu_x86_cpuid()
6910 *edx = 0; in cpu_x86_cpuid()
6915 if (count == 0) { in cpu_x86_cpuid()
6921 case 0x24: { in cpu_x86_cpuid()
6922 *eax = 0; in cpu_x86_cpuid()
6923 *ebx = 0; in cpu_x86_cpuid()
6924 *ecx = 0; in cpu_x86_cpuid()
6925 *edx = 0; in cpu_x86_cpuid()
6926 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { in cpu_x86_cpuid()
6931 case 0x40000000: in cpu_x86_cpuid()
6938 *eax = 0x40000001; in cpu_x86_cpuid()
6939 *ebx = signature[0]; in cpu_x86_cpuid()
6943 *eax = 0; in cpu_x86_cpuid()
6944 *ebx = 0; in cpu_x86_cpuid()
6945 *ecx = 0; in cpu_x86_cpuid()
6946 *edx = 0; in cpu_x86_cpuid()
6949 case 0x40000001: in cpu_x86_cpuid()
6950 *eax = 0; in cpu_x86_cpuid()
6951 *ebx = 0; in cpu_x86_cpuid()
6952 *ecx = 0; in cpu_x86_cpuid()
6953 *edx = 0; in cpu_x86_cpuid()
6955 case 0x80000000: in cpu_x86_cpuid()
6961 case 0x80000001: in cpu_x86_cpuid()
6963 *ebx = 0; in cpu_x86_cpuid()
6983 case 0x80000002: in cpu_x86_cpuid()
6984 case 0x80000003: in cpu_x86_cpuid()
6985 case 0x80000004: in cpu_x86_cpuid()
6986 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; in cpu_x86_cpuid()
6987 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; in cpu_x86_cpuid()
6988 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; in cpu_x86_cpuid()
6989 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; in cpu_x86_cpuid()
6991 case 0x80000005: in cpu_x86_cpuid()
6994 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); in cpu_x86_cpuid()
7004 case 0x80000006: in cpu_x86_cpuid()
7007 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); in cpu_x86_cpuid()
7023 case 0x80000007: in cpu_x86_cpuid()
7024 *eax = 0; in cpu_x86_cpuid()
7026 *ecx = 0; in cpu_x86_cpuid()
7029 case 0x80000008: in cpu_x86_cpuid()
7043 * Bits 7:0 is "The number of threads in the package is NC+1" in cpu_x86_cpuid()
7048 *ecx = 0; in cpu_x86_cpuid()
7050 *edx = 0; in cpu_x86_cpuid()
7052 case 0x8000000A: in cpu_x86_cpuid()
7054 *eax = 0x00000001; /* SVM Revision */ in cpu_x86_cpuid()
7055 *ebx = 0x00000010; /* nr of ASIDs */ in cpu_x86_cpuid()
7056 *ecx = 0; in cpu_x86_cpuid()
7059 *eax = 0; in cpu_x86_cpuid()
7060 *ebx = 0; in cpu_x86_cpuid()
7061 *ecx = 0; in cpu_x86_cpuid()
7062 *edx = 0; in cpu_x86_cpuid()
7065 case 0x8000001D: in cpu_x86_cpuid()
7066 *eax = 0; in cpu_x86_cpuid()
7072 case 0: /* L1 dcache info */ in cpu_x86_cpuid()
7089 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
7096 case 0x8000001E: in cpu_x86_cpuid()
7100 *eax = 0; in cpu_x86_cpuid()
7101 *ebx = 0; in cpu_x86_cpuid()
7102 *ecx = 0; in cpu_x86_cpuid()
7103 *edx = 0; in cpu_x86_cpuid()
7106 case 0x80000022: in cpu_x86_cpuid()
7107 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
7113 R_EBX) & 0xf; in cpu_x86_cpuid()
7116 case 0xC0000000: in cpu_x86_cpuid()
7118 *ebx = 0; in cpu_x86_cpuid()
7119 *ecx = 0; in cpu_x86_cpuid()
7120 *edx = 0; in cpu_x86_cpuid()
7122 case 0xC0000001: in cpu_x86_cpuid()
7125 *ebx = 0; in cpu_x86_cpuid()
7126 *ecx = 0; in cpu_x86_cpuid()
7129 case 0xC0000002: in cpu_x86_cpuid()
7130 case 0xC0000003: in cpu_x86_cpuid()
7131 case 0xC0000004: in cpu_x86_cpuid()
7133 *eax = 0; in cpu_x86_cpuid()
7134 *ebx = 0; in cpu_x86_cpuid()
7135 *ecx = 0; in cpu_x86_cpuid()
7136 *edx = 0; in cpu_x86_cpuid()
7138 case 0x8000001F: in cpu_x86_cpuid()
7139 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
7141 *eax = 0x2; in cpu_x86_cpuid()
7142 *eax |= sev_es_enabled() ? 0x8 : 0; in cpu_x86_cpuid()
7143 *eax |= sev_snp_enabled() ? 0x10 : 0; in cpu_x86_cpuid()
7144 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ in cpu_x86_cpuid()
7145 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ in cpu_x86_cpuid()
7148 case 0x80000021: in cpu_x86_cpuid()
7149 *eax = *ebx = *ecx = *edx = 0; in cpu_x86_cpuid()
7155 *eax = 0; in cpu_x86_cpuid()
7156 *ebx = 0; in cpu_x86_cpuid()
7157 *ecx = 0; in cpu_x86_cpuid()
7158 *edx = 0; in cpu_x86_cpuid()
7167 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; in x86_cpu_set_sgxlepubkeyhash()
7168 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; in x86_cpu_set_sgxlepubkeyhash()
7169 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; in x86_cpu_set_sgxlepubkeyhash()
7170 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; in x86_cpu_set_sgxlepubkeyhash()
7205 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); in x86_cpu_reset_hold()
7214 env->int_ctl = 0; in x86_cpu_reset_hold()
7219 cpu_x86_update_cr0(env, 0x60000010); in x86_cpu_reset_hold()
7220 env->a20_mask = ~0x0; in x86_cpu_reset_hold()
7221 env->smbase = 0x30000; in x86_cpu_reset_hold()
7222 env->msr_smi_count = 0; in x86_cpu_reset_hold()
7224 env->idt.limit = 0xffff; in x86_cpu_reset_hold()
7225 env->gdt.limit = 0xffff; in x86_cpu_reset_hold()
7226 env->ldt.limit = 0xffff; in x86_cpu_reset_hold()
7228 env->tr.limit = 0xffff; in x86_cpu_reset_hold()
7231 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, in x86_cpu_reset_hold()
7234 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, in x86_cpu_reset_hold()
7237 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, in x86_cpu_reset_hold()
7240 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, in x86_cpu_reset_hold()
7243 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, in x86_cpu_reset_hold()
7246 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, in x86_cpu_reset_hold()
7250 env->eip = 0xfff0; in x86_cpu_reset_hold()
7253 env->eflags = 0x2; in x86_cpu_reset_hold()
7256 for (i = 0; i < 8; i++) { in x86_cpu_reset_hold()
7259 cpu_set_fpuc(env, 0x37f); in x86_cpu_reset_hold()
7261 env->mxcsr = 0x1f80; in x86_cpu_reset_hold()
7263 env->xstate_bv = 0; in x86_cpu_reset_hold()
7265 env->pat = 0x0007040600070406ULL; in x86_cpu_reset_hold()
7269 * KVM handles TSC = 0 specially and thinks we are hot-plugging in x86_cpu_reset_hold()
7272 if (env->tsc != 0) { in x86_cpu_reset_hold()
7276 env->tsc = 0; in x86_cpu_reset_hold()
7284 memset(env->dr, 0, sizeof(env->dr)); in x86_cpu_reset_hold()
7290 cr4 = 0; in x86_cpu_reset_hold()
7321 * - IA32_MTRR_DEF_TYPE MSR.E = 0 in x86_cpu_reset_hold()
7322 * - IA32_MTRR_PHYSMASKn.V = 0 in x86_cpu_reset_hold()
7325 env->mtrr_deftype = 0; in x86_cpu_reset_hold()
7326 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); in x86_cpu_reset_hold()
7327 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); in x86_cpu_reset_hold()
7331 env->exception_pending = 0; in x86_cpu_reset_hold()
7332 env->exception_injected = 0; in x86_cpu_reset_hold()
7334 env->exception_payload = 0; in x86_cpu_reset_hold()
7339 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); in x86_cpu_reset_hold()
7372 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 in mce_init()
7376 (cpu->enable_lmce ? MCG_LMCE_P : 0); in mce_init()
7377 cenv->mcg_ctl = ~(uint64_t)0; in mce_init()
7378 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { in mce_init()
7379 cenv->mce_banks[bank * 4] = ~(uint64_t)0; in mce_init()
7397 uint32_t region = eax & 0xF0000000; in x86_cpu_adjust_feat_level()
7405 case 0x00000000: in x86_cpu_adjust_feat_level()
7408 case 0x80000000: in x86_cpu_adjust_feat_level()
7411 case 0xC0000000: in x86_cpu_adjust_feat_level()
7431 env->features[FEAT_XSAVE_XCR0_LO] = 0; in x86_cpu_enable_xsave_components()
7432 env->features[FEAT_XSAVE_XCR0_HI] = 0; in x86_cpu_enable_xsave_components()
7433 env->features[FEAT_XSAVE_XSS_LO] = 0; in x86_cpu_enable_xsave_components()
7434 env->features[FEAT_XSAVE_XSS_HI] = 0; in x86_cpu_enable_xsave_components()
7438 mask = 0; in x86_cpu_enable_xsave_components()
7439 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { in x86_cpu_enable_xsave_components()
7525 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_expand_features()
7537 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); in x86_cpu_expand_features()
7538 env->avx10_version = ebx & 0xff; in x86_cpu_expand_features()
7542 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { in x86_cpu_expand_features()
7557 env->features[FEAT_KVM] = 0; in x86_cpu_expand_features()
7562 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ in x86_cpu_expand_features()
7580 /* Intel Processor Trace requires CPUID[0x14] */ in x86_cpu_expand_features()
7583 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); in x86_cpu_expand_features()
7584 } else if (cpu->env.cpuid_min_level < 0x14) { in x86_cpu_expand_features()
7587 … "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); in x86_cpu_expand_features()
7592 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. in x86_cpu_expand_features()
7593 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect in x86_cpu_expand_features()
7594 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless in x86_cpu_expand_features()
7600 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); in x86_cpu_expand_features()
7603 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ in x86_cpu_expand_features()
7605 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); in x86_cpu_expand_features()
7608 /* SVM requires CPUID[0x8000000A] */ in x86_cpu_expand_features()
7610 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); in x86_cpu_expand_features()
7613 /* SEV requires CPUID[0x8000001F] */ in x86_cpu_expand_features()
7615 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); in x86_cpu_expand_features()
7619 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); in x86_cpu_expand_features()
7622 /* SGX requires CPUID[0x12] for EPC enumeration */ in x86_cpu_expand_features()
7624 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); in x86_cpu_expand_features()
7669 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_filter_features()
7683 x86_cpu_get_supported_cpuid(0x14, 0, in x86_cpu_filter_features()
7685 x86_cpu_get_supported_cpuid(0x14, 1, in x86_cpu_filter_features()
7710 x86_cpu_get_supported_cpuid(0x24, 0, in x86_cpu_filter_features()
7712 uint8_t version = ebx_0 & 0xff; in x86_cpu_filter_features()
7746 memset(cpu->hyperv_vendor_id, 0, 12); in x86_cpu_hyperv_realize()
7750 cpu->hyperv_interface_id[0] = 0x31237648; in x86_cpu_hyperv_realize()
7751 cpu->hyperv_interface_id[1] = 0; in x86_cpu_hyperv_realize()
7752 cpu->hyperv_interface_id[2] = 0; in x86_cpu_hyperv_realize()
7753 cpu->hyperv_interface_id[3] = 0; in x86_cpu_hyperv_realize()
7756 cpu->hyperv_limits[0] = 64; in x86_cpu_hyperv_realize()
7757 cpu->hyperv_limits[1] = 0; in x86_cpu_hyperv_realize()
7758 cpu->hyperv_limits[2] = 0; in x86_cpu_hyperv_realize()
7820 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " in x86_cpu_realizefn()
7821 "the host value (0x%x).", in x86_cpu_realizefn()
7871 cpu->guest_phys_bits = 0; in x86_cpu_realizefn()
7874 if (cpu->ucode_rev == 0) { in x86_cpu_realizefn()
7881 cpu->ucode_rev = 0x01000065; in x86_cpu_realizefn()
7883 cpu->ucode_rev = 0x100000000ULL; in x86_cpu_realizefn()
7917 * 0 means it was not explicitly set by the user (or by machine in x86_cpu_realizefn()
7921 if (cpu->phys_bits == 0) { in x86_cpu_realizefn()
7936 if (cpu->phys_bits != 0) { in x86_cpu_realizefn()
7940 if (cpu->guest_phys_bits != 0) { in x86_cpu_realizefn()
8164 esa->size = 0; in x86_cpu_post_initfn()
8253 return cpu->env.cr[0] & CR0_PG_MASK; in x86_cpu_get_paging_enabled()
8313 return 0; in x86_cpu_pending_interrupt()
8318 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; in x86_cpu_has_work()
8323 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; in x86_mmu_index_pl()
8340 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; in x86_mmu_index_kernel_pl()
8382 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); in x86_update_hflags()
8383 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & in x86_update_hflags()
8402 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || in x86_update_hflags()
8407 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; in x86_update_hflags()
8415 /* apic_id = 0 by default for *-user, see commit 9886e834 */
8416 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
8417 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
8418 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
8419 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0),
8420 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
8421 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
8437 HYPERV_FEAT_RELAXED, 0),
8439 HYPERV_FEAT_VAPIC, 0),
8441 HYPERV_FEAT_TIME, 0),
8443 HYPERV_FEAT_CRASH, 0),
8445 HYPERV_FEAT_RESET, 0),
8447 HYPERV_FEAT_VPINDEX, 0),
8449 HYPERV_FEAT_RUNTIME, 0),
8451 HYPERV_FEAT_SYNIC, 0),
8453 HYPERV_FEAT_STIMER, 0),
8455 HYPERV_FEAT_FREQUENCIES, 0),
8457 HYPERV_FEAT_REENLIGHTENMENT, 0),
8459 HYPERV_FEAT_TLBFLUSH, 0),
8461 HYPERV_FEAT_EVMCS, 0),
8463 HYPERV_FEAT_IPI, 0),
8465 HYPERV_FEAT_STIMER_DIRECT, 0),
8467 HYPERV_FEAT_AVIC, 0),
8469 HYPERV_FEAT_MSR_BITMAP, 0),
8471 HYPERV_FEAT_XMM_INPUT, 0),
8473 HYPERV_FEAT_TLBFLUSH_EXT, 0),
8475 HYPERV_FEAT_TLBFLUSH_DIRECT, 0),
8480 HYPERV_FEAT_SYNDBG, 0),
8487 0x3839),
8489 0x000A),
8491 0x0000),
8492 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
8493 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
8494 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
8500 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
8503 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
8510 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
8511 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
8512 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
8513 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
8514 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
8517 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
8650 for (w = 0; w < FEATURE_WORDS; w++) { in x86_cpu_common_class_init()
8652 for (bitnr = 0; bitnr < 64; bitnr++) { in x86_cpu_common_class_init()
8693 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { in x86_cpu_register_types()