83 #define CHECK_NOSHUF(VA, SIZE) \  argument
86             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
105 #define MEM_LOAD1s(DST, VA) \  argument
107         CHECK_NOSHUF(VA, 1); \
108         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
110 #define MEM_LOAD1u(DST, VA) \  argument
112         CHECK_NOSHUF(VA, 1); \
113         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
115 #define MEM_LOAD2s(DST, VA) \  argument
117         CHECK_NOSHUF(VA, 2); \
118         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
120 #define MEM_LOAD2u(DST, VA) \  argument
122         CHECK_NOSHUF(VA, 2); \
123         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
125 #define MEM_LOAD4s(DST, VA) \  argument
127         CHECK_NOSHUF(VA, 4); \
128         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
130 #define MEM_LOAD4u(DST, VA) \  argument
132         CHECK_NOSHUF(VA, 4); \
133         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
135 #define MEM_LOAD8u(DST, VA) \  argument
137         CHECK_NOSHUF(VA, 8); \
138         tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
146 #define MEM_STORE1(VA, DATA, SLOT) \  argument
147     MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
154 #define MEM_STORE2(VA, DATA, SLOT) \  argument
155     MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
162 #define MEM_STORE4(VA, DATA, SLOT) \  argument
163     MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
170 #define MEM_STORE8(VA, DATA, SLOT) \  argument
171     MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
173 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)  argument
174 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)  argument
175 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)  argument
176 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)  argument