Lines Matching +full:hexagon +full:- +full:linux +full:- +full:user
1 Hexagon is Qualcomm's very long instruction word (VLIW) digital signal
2 processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX
6 The following versions of the Hexagon core are supported
8 … https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-programmers-reference-manual-rev-aa
10 …https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-hvx-programmers-reference-manual-rev…
13 …-hexagon-automatic-translation-of-the-isa-manual-pseudcode-to-tiny-code-instructions-of-a-vliw-arc…
17 The qemu-hexagon implementation is a combination of qemu and the Hexagon
19 Hexagon-specific code are
21 qemu/target/hexagon
23 qemu/target/hexagon/imported
30 qemu/target/hexagon/idef-parser
31 Parser that, given the high-level definitions of an instruction,
34 qemu/linux-user/hexagon
35 Helpers for loading the ELF file and making Linux system calls,
41 target/hexagon/gen_semantics.c. This step produces
42 <BUILD_DIR>/target/hexagon/semantics_generated.pyinc.
44 header files in <BUILD_DIR>/target/hexagon
45 gen_opcodes_def.py -> opcodes_def_generated.h.inc
46 gen_printinsn.py -> printinsn_generated.h.inc
47 gen_op_attribs.py -> op_attribs_generated.h.inc
48 gen_helper_protos.py -> helper_protos_generated.h.inc
49 gen_tcg_funcs.py -> tcg_funcs_generated.c.inc
50 gen_tcg_func_table.py -> tcg_func_table_generated.c.inc
51 gen_helper_funcs.py -> helper_funcs_generated.c.inc
52 gen_idef_parser_funcs.py -> idef_parser_input.h
53 gen_analyze_funcs.py -> analyze_funcs_generated.c.inc
84 const int RdN = insn->regno[0];
85 TCGv RsV = hex_gpr[insn->regno[1]];
86 TCGv RtV = hex_gpr[insn->regno[2]];
108 This allows the code generator to override the auto-generated code. In some
135 address to helper functions. Here's an example for an HVX vector-add-word
139 Insn *insn __attribute__((unused)) = ctx->insn;
140 const int VdN = insn->regno[0];
145 const int VuN = insn->regno[1];
149 const int VvN = insn->regno[2];
160 functions from tcg-op-gvec.h. Here's the override for this instruction.
170 Insn *insn __attribute__((unused)) = ctx->insn;
171 const int VdN = insn->regno[0];
174 const int VuN = insn->regno[1];
177 const int VvN = insn->regno[2];
187 semantics can be short-circuited. If not, we initialize the result register for each
192 Step 1 is to run target/hexagon/gen_dectree_import.c to produce
193 <BUILD_DIR>/target/hexagon/iset.py
194 Step 2 is to import iset.py into target/hexagon/gen_decodetree.py to produce
195 <BUILD_DIR>/target/hexagon/normal_decode_generated
196 <BUILD_DIR>/target/hexagon/hvx_decode_generated
197 <BUILD_DIR>/target/hexagon/subinsn_*_decode_generated
199 <BUILD_DIR>/target/hexagon/decode_*_generated.c.inc
200 Step 4 is to import iset.py into target/hexagon/gen_trans_funcs.py to produce
201 <BUILD_DIR>/target/hexagon/decodetree_trans_funcs_generated.c.inc
214 The Hexagon arch lib relies heavily on macros for the instruction semantics.
226 gen_start_packet - initialize the data structures for packet semantics
227 gen_commit_packet - commit the register writes, stores, etc for a packet
228 decode_and_translate_packet - disassemble a packet and generate code
276 For Hexagon Vector eXtensions (HVX), the following fields are used
289 To track down nasty issues with Hexagon->TCG generation, we compare the
290 execution results with actual hardware running on a Hexagon Linux target.
291 Run qemu with the "-d cpu" option. Then, we can diff the results and figure
295 env->stack_adjust in translate.c. First, set this to zero and run qemu.
296 Then, change env->stack_adjust to the difference between the two stack
304 br translate.c:602 if ctx->base.pc_next == 0xdeadbeef
310 br helper_debug_start_packet if env->gpr[41] == 0xdeadbeef