target/avr/insn.decode

4 # Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
24 #   regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30]
26 %rd             4:5
27 %rr             9:1 0:4
32 %rr_a           0:4                         !function=to_regs_16_31_by_one
33 %rr_b           0:3                         !function=to_regs_16_23_by_one
35 %imm6           6:2 0:4
36 %imm8           8:4 0:4
38 %io_imm         9:2 0:4
39 %ldst_d_imm     13:1 10:2 0:3
66 COM             1001 010 rd:5 0000
67 NEG             1001 010 rd:5 0001
68 INC             1001 010 rd:5 0011
69 DEC             1001 010 rd:5 1010
72 MULSU           0000 0011 0 ... 0 ...       @fmul
73 FMUL            0000 0011 0 ... 1 ...       @fmul
74 FMULS           0000 0011 1 ... 0 ...       @fmul
82 # The 22-bit immediate is partially in the opcode word,
84 # complete 22-bit value.
85 %imm_call       4:5 0:1                     !function=append_16
104 SBRC            1111 110 rr:5 0 bit:3
105 SBRS            1111 111 rr:5 0 bit:3
106 SBIC            1001 1001 reg:5 bit:3
107 SBIS            1001 1011 reg:5 bit:3
116 %rr_d           0:4                         !function=to_regs_00_30_by_two
119 @ldst_d         .. . . .. . rd:5  . ...     &rd_imm     imm=%ldst_d_imm
121 # The 16-bit immediate is completely in the next word.
123 # the same trick and append to a zero-bit value.
125 @ldst_s         .... ... rd:5 ....          imm=0
131 LDX1            1001 000 rd:5 1100
132 LDX2            1001 000 rd:5 1101
133 LDX3            1001 000 rd:5 1110
134 LDY2            1001 000 rd:5 1001
135 LDY3            1001 000 rd:5 1010
136 LDZ2            1001 000 rd:5 0001
137 LDZ3            1001 000 rd:5 0010
138 LDDY            10 . 0 .. 0 ..... 1 ...     @ldst_d
139 LDDZ            10 . 0 .. 0 ..... 0 ...     @ldst_d
141 STX1            1001 001 rr:5 1100
142 STX2            1001 001 rr:5 1101
143 STX3            1001 001 rr:5 1110
144 STY2            1001 001 rd:5 1001
145 STY3            1001 001 rd:5 1010
146 STZ2            1001 001 rd:5 0001
147 STZ3            1001 001 rd:5 0010
148 STDY            10 . 0 .. 1 ..... 1 ...     @ldst_d
149 STDZ            10 . 0 .. 1 ..... 0 ...     @ldst_d
151 LPM2            1001 000 rd:5 0100
152 LPMX            1001 000 rd:5 0101
154 ELPM2           1001 000 rd:5 0110
155 ELPMX           1001 000 rd:5 0111
158 IN              1011 0 .. ..... ....        @io_rd_imm
160 PUSH            1001 001 rd:5 1111
161 POP             1001 000 rd:5 1111
162 XCH             1001 001 rd:5 0100
163 LAC             1001 001 rd:5 0110
164 LAS             1001 001 rd:5 0101
165 LAT             1001 001 rd:5 0111
168 # Bit and Bit-test Instructions
170 LSR             1001 010 rd:5 0110
171 ROR             1001 010 rd:5 0111
172 ASR             1001 010 rd:5 0101
173 SWAP            1001 010 rd:5 0010
174 SBI             1001 1010 reg:5 bit:3
175 CBI             1001 1000 reg:5 bit:3
176 BST             1111 101 rd:5 0 bit:3
177 BLD             1111 100 rd:5 0 bit:3
178 BSET            1001 0100 0 bit:3 1000