Lines Matching +full:cpu +full:- +full:2
2 #include "cpu.h"
3 #include "qemu/error-report.h"
8 #include "cpu-features.h"
9 #include "migration/cpu.h"
14 ARMCPU *cpu = opaque; in vfp_needed() local
16 return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) in vfp_needed()
17 ? cpu_isar_feature(aa64_fp_simd, cpu) in vfp_needed()
18 : cpu_isar_feature(aa32_vfp_simd, cpu)); in vfp_needed()
27 * cpu/vfp/fpcr_fpsr subsection, and we will send a 0 for the old in vfp_fpcr_fpsr_needed()
28 * FPSCR field in cpu/vfp. in vfp_fpcr_fpsr_needed()
31 * send that value as the cpu/vfp FPSCR field, and don't send the in vfp_fpcr_fpsr_needed()
32 * cpu/vfp/fpcr_fpsr subsection. in vfp_fpcr_fpsr_needed()
34 * On incoming migration, if the cpu/vfp FPSCR field is non-zero we in vfp_fpcr_fpsr_needed()
36 * (The subsection will never be present with a non-zero FPSCR field, in vfp_fpcr_fpsr_needed()
43 ARMCPU *cpu = opaque; in vfp_fpcr_fpsr_needed() local
44 CPUARMState *env = &cpu->env; in vfp_fpcr_fpsr_needed()
53 ARMCPU *cpu = opaque; in get_fpscr() local
54 CPUARMState *env = &cpu->env; in get_fpscr()
67 ARMCPU *cpu = opaque; in put_fpscr() local
68 CPUARMState *env = &cpu->env; in put_fpscr()
84 ARMCPU *cpu = opaque; in get_fpcr() local
85 CPUARMState *env = &cpu->env; in get_fpcr()
95 ARMCPU *cpu = opaque; in put_fpcr() local
96 CPUARMState *env = &cpu->env; in put_fpcr()
111 ARMCPU *cpu = opaque; in get_fpsr() local
112 CPUARMState *env = &cpu->env; in get_fpsr()
122 ARMCPU *cpu = opaque; in put_fpsr() local
123 CPUARMState *env = &cpu->env; in put_fpsr()
136 .name = "cpu/vfp/fpcr_fpsr",
162 .name = "cpu/vfp",
168 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2),
169 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2),
170 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2),
171 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2),
172 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2),
173 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2),
174 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2),
175 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2),
176 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2),
177 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2),
178 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2),
179 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2),
180 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2),
181 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2),
182 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2),
183 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2),
184 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2),
185 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2),
186 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2),
187 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2),
188 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2),
189 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2),
190 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2),
191 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2),
192 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2),
193 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2),
194 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2),
195 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2),
196 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2),
197 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2),
198 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2),
199 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2),
206 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
225 ARMCPU *cpu = opaque; in iwmmxt_needed() local
226 CPUARMState *env = &cpu->env; in iwmmxt_needed()
232 .name = "cpu/iwmmxt",
244 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
251 ARMCPU *cpu = opaque; in sve_needed() local
253 return cpu_isar_feature(aa64_sve, cpu); in sve_needed()
258 .name = "cpu/sve/zreg_hi",
262 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2),
268 .name = "cpu/sve/preg",
272 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8),
278 .name = "cpu/sve",
296 VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2),
303 ARMCPU *cpu = opaque; in za_needed() local
307 * It will be zeroed when ZA storage is re-enabled. in za_needed()
309 return FIELD_EX64(cpu->env.svcr, SVCR, ZA); in za_needed()
313 .name = "cpu/sme",
327 ARMCPU *cpu = opaque; in serror_needed() local
328 CPUARMState *env = &cpu->env; in serror_needed()
330 return env->serror.pending != 0; in serror_needed()
334 .name = "cpu/serror",
352 .name = "cpu/irq-line-state",
364 ARMCPU *cpu = opaque; in wfxt_timer_needed() local
367 return cpu->wfxt_timer; in wfxt_timer_needed()
371 .name = "cpu/wfxt-timer",
383 ARMCPU *cpu = opaque; in m_needed() local
384 CPUARMState *env = &cpu->env; in m_needed()
390 .name = "cpu/m/faultmask-primask",
406 * just non-secure, we transfer both banks here rather than putting
407 * the secure banked version in the m-security subsection.
411 ARMCPU *cpu = opaque; in csselr_vmstate_validate() local
413 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK in csselr_vmstate_validate()
414 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; in csselr_vmstate_validate()
419 ARMCPU *cpu = opaque; in m_csselr_needed() local
421 return !arm_v7m_csselr_razwi(cpu); in m_csselr_needed()
425 .name = "cpu/m/csselr",
437 .name = "cpu/m/scr",
448 .name = "cpu/m/other-sp",
460 ARMCPU *cpu = opaque; in m_v8m_needed() local
461 CPUARMState *env = &cpu->env; in m_v8m_needed()
467 .name = "cpu/m/v8m",
479 .name = "cpu/m/fp",
495 ARMCPU *cpu = opaque; in mve_needed() local
497 return cpu_isar_feature(aa32_mve, cpu); in mve_needed()
501 .name = "cpu/m/mve",
513 .name = "cpu/m",
545 ARMCPU *cpu = opaque; in thumb2ee_needed() local
546 CPUARMState *env = &cpu->env; in thumb2ee_needed()
552 .name = "cpu/thumb2ee",
565 ARMCPU *cpu = opaque; in pmsav7_needed() local
566 CPUARMState *env = &cpu->env; in pmsav7_needed()
575 ARMCPU *cpu = opaque; in pmsav7_rgnr_vmstate_validate() local
577 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; in pmsav7_rgnr_vmstate_validate()
581 .name = "cpu/pmsav7",
599 ARMCPU *cpu = opaque; in pmsav7_rnr_needed() local
600 CPUARMState *env = &cpu->env; in pmsav7_rnr_needed()
610 .name = "cpu/pmsav7-rnr",
622 ARMCPU *cpu = opaque; in pmsav8_needed() local
623 CPUARMState *env = &cpu->env; in pmsav8_needed()
631 ARMCPU *cpu = opaque; in pmsav8r_needed() local
632 CPUARMState *env = &cpu->env; in pmsav8r_needed()
640 .name = "cpu/pmsav8/pmsav8r",
654 .name = "cpu/pmsav8",
675 ARMCPU *cpu = opaque; in s_rnr_vmstate_validate() local
677 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; in s_rnr_vmstate_validate()
682 ARMCPU *cpu = opaque; in sau_rnr_vmstate_validate() local
684 return cpu->env.sau.rnr < cpu->sau_sregion; in sau_rnr_vmstate_validate()
689 ARMCPU *cpu = opaque; in m_security_needed() local
690 CPUARMState *env = &cpu->env; in m_security_needed()
696 .name = "cpu/m-security",
731 /* AIRCR is not secure-only, but our implementation is R/O if the
742 ARMCPU *cpu = opaque; in get_cpsr() local
743 CPUARMState *env = &cpu->env; in get_cpsr()
768 * and PRIMASK in env->daif. For a new QEMU, the data is in get_cpsr()
772 env->v7m.faultmask[M_REG_NS] = 1; in get_cpsr()
775 env->v7m.primask[M_REG_NS] = 1; in get_cpsr()
784 env->aarch64 = ((val & PSTATE_nRW) == 0); in get_cpsr()
798 ARMCPU *cpu = opaque; in put_cpsr() local
799 CPUARMState *env = &cpu->env; in put_cpsr()
824 ARMCPU *cpu = opaque; in get_power() local
826 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; in get_power()
833 ARMCPU *cpu = opaque; in put_power() local
837 if (cpu->power_state == PSCI_ON || in put_power()
838 cpu->power_state == PSCI_OFF) { in put_power()
839 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; in put_power()
855 ARMCPU *cpu = opaque; in cpu_pre_save() local
858 pmu_op_start(&cpu->env); in cpu_pre_save()
862 if (!write_kvmstate_to_list(cpu)) { in cpu_pre_save()
871 kvm_arm_cpu_pre_save(cpu); in cpu_pre_save()
873 if (!write_cpustate_to_list(cpu, false)) { in cpu_pre_save()
879 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; in cpu_pre_save()
880 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, in cpu_pre_save()
881 cpu->cpreg_array_len * sizeof(uint64_t)); in cpu_pre_save()
882 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, in cpu_pre_save()
883 cpu->cpreg_array_len * sizeof(uint64_t)); in cpu_pre_save()
890 ARMCPU *cpu = opaque; in cpu_post_save() local
893 pmu_op_finish(&cpu->env); in cpu_post_save()
901 ARMCPU *cpu = opaque; in cpu_pre_load() local
902 CPUARMState *env = &cpu->env; in cpu_pre_load()
914 * future architecture change makes the reset value non-zero. in cpu_pre_load()
919 * Pre-initialize irq_line_state to a value that's never valid as in cpu_pre_load()
921 * irq-line-state subsection in the incoming migration state. in cpu_pre_load()
923 env->irq_line_state = UINT32_MAX; in cpu_pre_load()
934 ARMCPU *cpu = opaque; in cpu_post_load() local
935 CPUARMState *env = &cpu->env; in cpu_post_load()
940 * send the irq-line-state subsection. A QEMU without it did not in cpu_post_load()
942 * so for TCG the line state matches the bits set in cs->interrupt_request. in cpu_post_load()
943 * For KVM the line state is not stored in cs->interrupt_request in cpu_post_load()
947 if (env->irq_line_state == UINT32_MAX) { in cpu_post_load()
948 CPUState *cs = CPU(cpu); in cpu_post_load()
950 env->irq_line_state = cs->interrupt_request & in cpu_post_load()
959 * The indexes list remains untouched -- we only inspect the in cpu_post_load()
964 for (i = 0, v = 0; i < cpu->cpreg_array_len in cpu_post_load()
965 && v < cpu->cpreg_vmstate_array_len; i++) { in cpu_post_load()
966 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { in cpu_post_load()
970 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { in cpu_post_load()
972 return -1; in cpu_post_load()
975 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; in cpu_post_load()
980 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { in cpu_post_load()
981 return -1; in cpu_post_load()
987 write_list_to_cpustate(cpu); in cpu_post_load()
988 kvm_arm_cpu_post_load(cpu); in cpu_post_load()
990 if (!write_list_to_cpustate(cpu)) { in cpu_post_load()
991 return -1; in cpu_post_load()
1000 if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { in cpu_post_load()
1001 return -1; in cpu_post_load()
1005 hw_breakpoint_update_all(cpu); in cpu_post_load()
1006 hw_watchpoint_update_all(cpu); in cpu_post_load()
1011 * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; in cpu_post_load()
1014 if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { in cpu_post_load()
1015 if (extract32(env->v7m.fpdscr[M_REG_NS], in cpu_post_load()
1017 extract32(env->v7m.fpdscr[M_REG_S], in cpu_post_load()
1019 return -1; in cpu_post_load()
1035 .name = "cpu",
1062 /* The length-check must come before the arrays to avoid