Lines Matching +full:cpu +full:- +full:2
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
25 #include "exec/address-spaces.h"
28 #include "qemu/main-loop.h"
30 #include "arm-powerctl.h"
31 #include "target/arm/cpu.h"
184 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
185 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
186 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
188 #define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1)
192 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
193 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
208 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)
217 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)
218 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)
229 #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2)
230 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4)
231 #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5)
232 #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6)
233 #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7)
234 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4)
235 #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5)
236 #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6)
237 #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7)
238 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4)
239 #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5)
240 #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6)
241 #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7)
242 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4)
243 #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5)
244 #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6)
245 #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7)
246 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4)
247 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5)
248 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6)
249 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7)
250 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4)
251 #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5)
252 #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6)
253 #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7)
254 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4)
255 #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5)
256 #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6)
257 #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7)
258 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4)
259 #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5)
260 #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6)
261 #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7)
262 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4)
263 #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5)
264 #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6)
265 #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7)
266 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4)
267 #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5)
268 #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6)
269 #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7)
270 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4)
271 #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5)
272 #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6)
273 #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7)
274 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4)
275 #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5)
276 #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6)
277 #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7)
278 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4)
279 #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5)
280 #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6)
281 #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7)
282 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4)
283 #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5)
284 #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6)
285 #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7)
286 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4)
287 #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5)
288 #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6)
289 #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7)
290 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4)
291 #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5)
292 #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
293 #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
299 #define TMR_CTL_ISTATUS (1 << 2)
301 static void hvf_wfi(CPUState *cpu);
330 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) },
365 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) },
404 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) },
405 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 5) },
406 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 6) },
407 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 7) },
409 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) },
410 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 5) },
411 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 6) },
412 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 7) },
414 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) },
415 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 5) },
416 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 6) },
417 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 7) },
419 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) },
420 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 5) },
421 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 6) },
422 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 7) },
424 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) },
425 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) },
426 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) },
427 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) },
429 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) },
430 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 5) },
431 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 6) },
432 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 7) },
434 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) },
435 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 5) },
436 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 6) },
437 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 7) },
439 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) },
440 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 5) },
441 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 6) },
442 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 7) },
444 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) },
445 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 5) },
446 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 6) },
447 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 7) },
449 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) },
450 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 5) },
451 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 6) },
452 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 7) },
454 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) },
455 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 5) },
456 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 6) },
457 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 7) },
459 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) },
460 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 5) },
461 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 6) },
462 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 7) },
464 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) },
465 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 5) },
466 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 6) },
467 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 7) },
469 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) },
470 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 5) },
471 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 6) },
472 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 7) },
474 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) },
475 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 5) },
476 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 6) },
477 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 7) },
479 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) },
480 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 5) },
481 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 6) },
482 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 7) },
489 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
504 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
507 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
509 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
510 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
511 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
512 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
514 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
515 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
516 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
517 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
518 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
519 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
520 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
521 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
522 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
523 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
530 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
533 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
539 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
540 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
543 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
547 int hvf_get_registers(CPUState *cpu) in hvf_get_registers() argument
549 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_get_registers()
550 CPUARMState *env = &arm_cpu->env; in hvf_get_registers()
557 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); in hvf_get_registers()
563 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_get_registers()
570 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); in hvf_get_registers()
575 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); in hvf_get_registers()
579 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); in hvf_get_registers()
584 if (hvf_sreg_match[i].cp_idx == -1) { in hvf_get_registers()
588 if (cpu->accel->guest_debug_enabled) { in hvf_get_registers()
665 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); in hvf_get_registers()
668 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; in hvf_get_registers()
674 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); in hvf_get_registers()
677 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; in hvf_get_registers()
686 int hvf_put_registers(CPUState *cpu) in hvf_put_registers() argument
688 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_put_registers()
689 CPUARMState *env = &arm_cpu->env; in hvf_put_registers()
697 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); in hvf_put_registers()
703 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_put_registers()
708 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); in hvf_put_registers()
711 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); in hvf_put_registers()
714 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); in hvf_put_registers()
721 if (hvf_sreg_match[i].cp_idx == -1) { in hvf_put_registers()
725 if (cpu->accel->guest_debug_enabled) { in hvf_put_registers()
801 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; in hvf_put_registers()
802 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); in hvf_put_registers()
806 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); in hvf_put_registers()
812 static void flush_cpu_state(CPUState *cpu) in flush_cpu_state() argument
814 if (cpu->accel->dirty) { in flush_cpu_state()
815 hvf_put_registers(cpu); in flush_cpu_state()
816 cpu->accel->dirty = false; in flush_cpu_state()
820 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) in hvf_set_reg() argument
824 flush_cpu_state(cpu); in hvf_set_reg()
827 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); in hvf_set_reg()
832 static uint64_t hvf_get_reg(CPUState *cpu, int rt) in hvf_get_reg() argument
837 flush_cpu_state(cpu); in hvf_get_reg()
840 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); in hvf_get_reg()
881 ahcf->dtb_compatible = "arm,arm-v8"; in hvf_arm_get_host_cpu_features()
882 ahcf->features = (1ULL << ARM_FEATURE_V8) | in hvf_arm_get_host_cpu_features()
897 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); in hvf_arm_get_host_cpu_features()
905 * - make sure that the SME state is correctly handled in the in hvf_arm_get_host_cpu_features()
907 * - get the SME-specific CPU properties to work with accelerators in hvf_arm_get_host_cpu_features()
909 * - fix any assumptions we made that SME implies SVE (since in hvf_arm_get_host_cpu_features()
914 ahcf->isar = host_isar; in hvf_arm_get_host_cpu_features()
920 ahcf->reset_sctlr = 0x30100180; in hvf_arm_get_host_cpu_features()
926 ahcf->reset_sctlr |= 0x00800000; in hvf_arm_get_host_cpu_features()
960 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) in hvf_arm_set_cpu_features_from_host() argument
969 cpu->host_cpu_probe_failed = true; in hvf_arm_set_cpu_features_from_host()
974 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; in hvf_arm_set_cpu_features_from_host()
975 cpu->isar = arm_host_cpu_features.isar; in hvf_arm_set_cpu_features_from_host()
976 cpu->env.features = arm_host_cpu_features.features; in hvf_arm_set_cpu_features_from_host()
977 cpu->midr = arm_host_cpu_features.midr; in hvf_arm_set_cpu_features_from_host()
978 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; in hvf_arm_set_cpu_features_from_host()
981 void hvf_arch_vcpu_destroy(CPUState *cpu) in hvf_arch_vcpu_destroy() argument
1004 int hvf_arch_init_vcpu(CPUState *cpu) in hvf_arch_init_vcpu() argument
1006 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_arch_init_vcpu()
1007 CPUARMState *env = &arm_cpu->env; in hvf_arch_init_vcpu()
1014 env->aarch64 = true; in hvf_arch_init_vcpu()
1015 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); in hvf_arch_init_vcpu()
1018 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, in hvf_arch_init_vcpu()
1020 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, in hvf_arch_init_vcpu()
1022 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, in hvf_arch_init_vcpu()
1023 arm_cpu->cpreg_vmstate_indexes, in hvf_arch_init_vcpu()
1025 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, in hvf_arch_init_vcpu()
1026 arm_cpu->cpreg_vmstate_values, in hvf_arch_init_vcpu()
1029 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); in hvf_arch_init_vcpu()
1036 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); in hvf_arch_init_vcpu()
1038 assert(!(ri->type & ARM_CP_NO_RAW)); in hvf_arch_init_vcpu()
1040 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); in hvf_arch_init_vcpu()
1042 hvf_sreg_match[i].cp_idx = -1; in hvf_arch_init_vcpu()
1045 arm_cpu->cpreg_array_len = sregs_cnt; in hvf_arch_init_vcpu()
1046 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; in hvf_arch_init_vcpu()
1051 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, in hvf_arch_init_vcpu()
1052 arm_cpu->midr); in hvf_arch_init_vcpu()
1055 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, in hvf_arch_init_vcpu()
1056 arm_cpu->mp_affinity); in hvf_arch_init_vcpu()
1059 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); in hvf_arch_init_vcpu()
1061 pfr |= env->gicv3state ? (1 << 24) : 0; in hvf_arch_init_vcpu()
1062 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); in hvf_arch_init_vcpu()
1066 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, in hvf_arch_init_vcpu()
1067 &arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1070 clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1071 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, in hvf_arch_init_vcpu()
1072 arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1078 void hvf_kick_vcpu_thread(CPUState *cpu) in hvf_kick_vcpu_thread() argument
1080 cpus_kick_thread(cpu); in hvf_kick_vcpu_thread()
1081 hv_vcpus_exit(&cpu->accel->fd, 1); in hvf_kick_vcpu_thread()
1084 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, in hvf_raise_exception() argument
1087 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_raise_exception()
1088 CPUARMState *env = &arm_cpu->env; in hvf_raise_exception()
1090 cpu->exception_index = excp; in hvf_raise_exception()
1091 env->exception.target_el = 1; in hvf_raise_exception()
1092 env->exception.syndrome = syndrome; in hvf_raise_exception()
1094 arm_cpu_do_interrupt(cpu); in hvf_raise_exception()
1107 * -1 when the PSCI call is unknown,
1109 static bool hvf_handle_psci_call(CPUState *cpu) in hvf_handle_psci_call() argument
1111 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_handle_psci_call()
1112 CPUARMState *env = &arm_cpu->env; in hvf_handle_psci_call()
1114 env->xregs[0], in hvf_handle_psci_call()
1115 env->xregs[1], in hvf_handle_psci_call()
1116 env->xregs[2], in hvf_handle_psci_call()
1117 env->xregs[3] in hvf_handle_psci_call()
1127 trace_hvf_psci_call(param[0], param[1], param[2], param[3], in hvf_handle_psci_call()
1141 switch (param[2]) { in hvf_handle_psci_call()
1150 ret = target_cpu->power_state; in hvf_handle_psci_call()
1162 * call, so power the CPU off now so it doesn't execute in hvf_handle_psci_call()
1175 entry = param[2]; in hvf_handle_psci_call()
1193 env->xregs[0] = 0; in hvf_handle_psci_call()
1194 hvf_wfi(cpu); in hvf_handle_psci_call()
1229 env->xregs[0] = ret; in hvf_handle_psci_call()
1252 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) in hvf_sysreg_read_cp() argument
1254 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_read_cp()
1255 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_read_cp()
1258 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); in hvf_sysreg_read_cp()
1260 if (ri->accessfn) { in hvf_sysreg_read_cp()
1261 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { in hvf_sysreg_read_cp()
1265 if (ri->type & ARM_CP_CONST) { in hvf_sysreg_read_cp()
1266 *val = ri->resetvalue; in hvf_sysreg_read_cp()
1267 } else if (ri->readfn) { in hvf_sysreg_read_cp()
1268 *val = ri->readfn(env, ri); in hvf_sysreg_read_cp()
1272 trace_hvf_vgic_read(ri->name, *val); in hvf_sysreg_read_cp()
1279 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) in hvf_sysreg_read() argument
1281 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_read()
1282 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_read()
1287 *val = env->cp15.c9_pmcr; in hvf_sysreg_read()
1291 *val = env->cp15.c15_ccnt; in hvf_sysreg_read()
1295 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1298 *val = env->cp15.c9_pmovsr; in hvf_sysreg_read()
1301 *val = env->cp15.c9_pmselr; in hvf_sysreg_read()
1304 *val = env->cp15.c9_pminten; in hvf_sysreg_read()
1307 *val = env->cp15.pmccfiltr_el0; in hvf_sysreg_read()
1310 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1313 *val = env->cp15.c9_pmuserenr; in hvf_sysreg_read()
1329 *val = env->cp15.oslsr_el1; in hvf_sysreg_read()
1360 if (hvf_sysreg_read_cp(cpu, reg, val)) { in hvf_sysreg_read()
1380 *val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1398 *val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1416 *val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1434 *val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1444 cpu_synchronize_state(cpu); in hvf_sysreg_read()
1445 trace_hvf_unhandled_sysreg_read(env->pc, reg, in hvf_sysreg_read()
1451 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_sysreg_read()
1457 ARMCPU *cpu = env_archcpu(env); in pmu_update_irq() local
1458 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq()
1459 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq()
1476 enabled = (env->cp15.c9_pmcr & PMCRE) && in pmu_counter_enabled()
1477 (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
1480 filter = env->cp15.pmccfiltr_el0; in pmu_counter_enabled()
1482 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
1514 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { in pmswinc_write()
1519 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; in pmswinc_write()
1521 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { in pmswinc_write()
1522 env->cp15.c9_pmovsr |= (1 << i); in pmswinc_write()
1526 env->cp15.c14_pmevcntr[i] = new_pmswinc; in pmswinc_write()
1531 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) in hvf_sysreg_write_cp() argument
1533 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_write_cp()
1534 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_write_cp()
1537 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); in hvf_sysreg_write_cp()
1540 if (ri->accessfn) { in hvf_sysreg_write_cp()
1541 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { in hvf_sysreg_write_cp()
1545 if (ri->writefn) { in hvf_sysreg_write_cp()
1546 ri->writefn(env, ri, val); in hvf_sysreg_write_cp()
1551 trace_hvf_vgic_write(ri->name, val); in hvf_sysreg_write_cp()
1558 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) in hvf_sysreg_write() argument
1560 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_write()
1561 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_write()
1575 env->cp15.c15_ccnt = val; in hvf_sysreg_write()
1583 env->cp15.c15_ccnt = 0; in hvf_sysreg_write()
1589 env->cp15.c14_pmevcntr[i] = 0; in hvf_sysreg_write()
1593 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in hvf_sysreg_write()
1594 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); in hvf_sysreg_write()
1599 env->cp15.c9_pmuserenr = val & 0xf; in hvf_sysreg_write()
1602 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); in hvf_sysreg_write()
1605 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); in hvf_sysreg_write()
1609 env->cp15.c9_pminten |= val; in hvf_sysreg_write()
1614 env->cp15.c9_pmovsr &= ~val; in hvf_sysreg_write()
1623 env->cp15.c9_pmselr = val & 0x1f; in hvf_sysreg_write()
1627 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; in hvf_sysreg_write()
1635 env->cp15.oslsr_el1 = val & 1; in hvf_sysreg_write()
1673 if (hvf_sysreg_write_cp(cpu, reg, val)) { in hvf_sysreg_write()
1678 env->cp15.mdscr_el1 = val; in hvf_sysreg_write()
1696 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1714 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1732 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1750 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1754 cpu_synchronize_state(cpu); in hvf_sysreg_write()
1755 trace_hvf_unhandled_sysreg_write(env->pc, reg, in hvf_sysreg_write()
1761 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_sysreg_write()
1765 static int hvf_inject_interrupts(CPUState *cpu) in hvf_inject_interrupts() argument
1767 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { in hvf_inject_interrupts()
1769 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, in hvf_inject_interrupts()
1773 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { in hvf_inject_interrupts()
1775 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, in hvf_inject_interrupts()
1788 return mach_absolute_time() - hvf_state->vtimer_offset; in hvf_vtimer_val_raw()
1801 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) in hvf_wait_for_ipi() argument
1807 qatomic_set_mb(&cpu->thread_kicked, false); in hvf_wait_for_ipi()
1809 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); in hvf_wait_for_ipi()
1813 static void hvf_wfi(CPUState *cpu) in hvf_wfi() argument
1815 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_wfi()
1825 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { in hvf_wfi()
1830 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); in hvf_wfi()
1833 if (!(ctl & 1) || (ctl & 2)) { in hvf_wfi()
1835 hvf_wait_for_ipi(cpu, NULL); in hvf_wfi()
1839 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); in hvf_wfi()
1842 ticks_to_sleep = cval - hvf_vtimer_val(); in hvf_wfi()
1849 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); in hvf_wfi()
1854 * so that we can satisfy fast timer requests on the same CPU. in hvf_wfi()
1855 * Measurements on M1 show the sweet spot to be ~2ms. in hvf_wfi()
1857 if (!seconds && nanos < (2 * SCALE_MS)) { in hvf_wfi()
1862 hvf_wait_for_ipi(cpu, &ts); in hvf_wfi()
1865 static void hvf_sync_vtimer(CPUState *cpu) in hvf_sync_vtimer() argument
1867 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sync_vtimer()
1872 if (!cpu->accel->vtimer_masked) { in hvf_sync_vtimer()
1877 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); in hvf_sync_vtimer()
1882 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); in hvf_sync_vtimer()
1886 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); in hvf_sync_vtimer()
1887 cpu->accel->vtimer_masked = false; in hvf_sync_vtimer()
1891 int hvf_vcpu_exec(CPUState *cpu) in hvf_vcpu_exec() argument
1893 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_vcpu_exec()
1894 CPUARMState *env = &arm_cpu->env; in hvf_vcpu_exec()
1896 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; in hvf_vcpu_exec()
1900 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && in hvf_vcpu_exec()
1901 hvf_inject_interrupts(cpu)) { in hvf_vcpu_exec()
1905 if (cpu->halted) { in hvf_vcpu_exec()
1909 flush_cpu_state(cpu); in hvf_vcpu_exec()
1912 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); in hvf_vcpu_exec()
1915 uint64_t exit_reason = hvf_exit->reason; in hvf_vcpu_exec()
1916 uint64_t syndrome = hvf_exit->exception.syndrome; in hvf_vcpu_exec()
1926 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); in hvf_vcpu_exec()
1927 cpu->accel->vtimer_masked = true; in hvf_vcpu_exec()
1936 hvf_sync_vtimer(cpu); in hvf_vcpu_exec()
1942 if (!cpu->singlestep_enabled) { in hvf_vcpu_exec()
1943 error_report("EC_SOFTWARESTEP but single-stepping not enabled"); in hvf_vcpu_exec()
1950 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1952 if (!hvf_find_sw_breakpoint(cpu, env->pc)) { in hvf_vcpu_exec()
1953 /* Re-inject into the guest */ in hvf_vcpu_exec()
1955 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); in hvf_vcpu_exec()
1962 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1964 if (!find_hw_breakpoint(cpu, env->pc)) { in hvf_vcpu_exec()
1972 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1975 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); in hvf_vcpu_exec()
1979 cpu->watchpoint_hit = wp; in hvf_vcpu_exec()
1993 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, in hvf_vcpu_exec()
1994 hvf_exit->exception.physical_address, isv, in hvf_vcpu_exec()
2006 val = hvf_get_reg(cpu, srt); in hvf_vcpu_exec()
2008 hvf_exit->exception.physical_address, in hvf_vcpu_exec()
2012 hvf_exit->exception.physical_address, in hvf_vcpu_exec()
2017 hvf_set_reg(cpu, srt, val); in hvf_vcpu_exec()
2031 sysreg_ret = hvf_sysreg_read(cpu, reg, &val); in hvf_vcpu_exec()
2040 hvf_set_reg(cpu, rt, val); in hvf_vcpu_exec()
2043 val = hvf_get_reg(cpu, rt); in hvf_vcpu_exec()
2044 sysreg_ret = hvf_sysreg_write(cpu, reg, val); in hvf_vcpu_exec()
2053 hvf_wfi(cpu); in hvf_vcpu_exec()
2057 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2058 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { in hvf_vcpu_exec()
2059 if (!hvf_handle_psci_call(cpu)) { in hvf_vcpu_exec()
2060 trace_hvf_unknown_hvc(env->xregs[0]); in hvf_vcpu_exec()
2061 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ in hvf_vcpu_exec()
2062 env->xregs[0] = -1; in hvf_vcpu_exec()
2065 trace_hvf_unknown_hvc(env->xregs[0]); in hvf_vcpu_exec()
2066 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_vcpu_exec()
2070 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2071 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { in hvf_vcpu_exec()
2074 if (!hvf_handle_psci_call(cpu)) { in hvf_vcpu_exec()
2075 trace_hvf_unknown_smc(env->xregs[0]); in hvf_vcpu_exec()
2076 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ in hvf_vcpu_exec()
2077 env->xregs[0] = -1; in hvf_vcpu_exec()
2080 trace_hvf_unknown_smc(env->xregs[0]); in hvf_vcpu_exec()
2081 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_vcpu_exec()
2085 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2086 trace_hvf_exit(syndrome, ec, env->pc); in hvf_vcpu_exec()
2087 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); in hvf_vcpu_exec()
2093 flush_cpu_state(cpu); in hvf_vcpu_exec()
2095 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); in hvf_vcpu_exec()
2098 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); in hvf_vcpu_exec()
2101 /* Handle single-stepping over instructions which trigger a VM exit */ in hvf_vcpu_exec()
2102 if (cpu->singlestep_enabled) { in hvf_vcpu_exec()
2111 .name = "hvf-vtimer",
2126 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; in hvf_vm_state_change()
2130 s->vtimer_val = hvf_vtimer_val_raw(); in hvf_vm_state_change()
2136 hvf_state->vtimer_offset = mach_absolute_time(); in hvf_arch_init()
2147 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) in hvf_arch_insert_sw_breakpoint() argument
2149 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || in hvf_arch_insert_sw_breakpoint()
2150 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { in hvf_arch_insert_sw_breakpoint()
2151 return -EINVAL; in hvf_arch_insert_sw_breakpoint()
2156 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) in hvf_arch_remove_sw_breakpoint() argument
2160 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || in hvf_arch_remove_sw_breakpoint()
2162 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { in hvf_arch_remove_sw_breakpoint()
2163 return -EINVAL; in hvf_arch_remove_sw_breakpoint()
2178 return -ENOSYS; in hvf_arch_insert_hw_breakpoint()
2192 return -ENOSYS; in hvf_arch_remove_hw_breakpoint()
2211 static void hvf_put_gdbstub_debug_registers(CPUState *cpu) in hvf_put_gdbstub_debug_registers() argument
2218 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); in hvf_put_gdbstub_debug_registers()
2220 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); in hvf_put_gdbstub_debug_registers()
2224 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2226 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2232 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); in hvf_put_gdbstub_debug_registers()
2234 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); in hvf_put_gdbstub_debug_registers()
2238 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2240 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2249 static void hvf_put_guest_debug_registers(CPUState *cpu) in hvf_put_guest_debug_registers() argument
2251 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_put_guest_debug_registers()
2252 CPUARMState *env = &arm_cpu->env; in hvf_put_guest_debug_registers()
2257 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], in hvf_put_guest_debug_registers()
2258 env->cp15.dbgbcr[i]); in hvf_put_guest_debug_registers()
2260 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], in hvf_put_guest_debug_registers()
2261 env->cp15.dbgbvr[i]); in hvf_put_guest_debug_registers()
2266 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], in hvf_put_guest_debug_registers()
2267 env->cp15.dbgwcr[i]); in hvf_put_guest_debug_registers()
2269 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], in hvf_put_guest_debug_registers()
2270 env->cp15.dbgwvr[i]); in hvf_put_guest_debug_registers()
2275 static inline bool hvf_arm_hw_debug_active(CPUState *cpu) in hvf_arm_hw_debug_active() argument
2282 CPUState *cpu; in hvf_arch_set_traps() local
2288 CPU_FOREACH(cpu) { in hvf_arch_set_traps()
2289 should_enable_traps |= cpu->accel->guest_debug_enabled; in hvf_arch_set_traps()
2291 CPU_FOREACH(cpu) { in hvf_arch_set_traps()
2293 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, in hvf_arch_set_traps()
2298 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, in hvf_arch_set_traps()
2304 void hvf_arch_update_guest_debug(CPUState *cpu) in hvf_arch_update_guest_debug() argument
2306 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_arch_update_guest_debug()
2307 CPUARMState *env = &arm_cpu->env; in hvf_arch_update_guest_debug()
2310 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || in hvf_arch_update_guest_debug()
2311 hvf_sw_breakpoints_active(cpu) || in hvf_arch_update_guest_debug()
2312 hvf_arm_hw_debug_active(cpu); in hvf_arch_update_guest_debug()
2315 if (cpu->accel->guest_debug_enabled) { in hvf_arch_update_guest_debug()
2316 hvf_put_gdbstub_debug_registers(cpu); in hvf_arch_update_guest_debug()
2318 hvf_put_guest_debug_registers(cpu); in hvf_arch_update_guest_debug()
2321 cpu_synchronize_state(cpu); in hvf_arch_update_guest_debug()
2323 /* Enable/disable single-stepping */ in hvf_arch_update_guest_debug()
2324 if (cpu->singlestep_enabled) { in hvf_arch_update_guest_debug()
2325 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2326 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); in hvf_arch_update_guest_debug()
2329 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2330 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); in hvf_arch_update_guest_debug()
2334 if (hvf_arm_hw_debug_active(cpu)) { in hvf_arch_update_guest_debug()
2335 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2336 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); in hvf_arch_update_guest_debug()
2338 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2339 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); in hvf_arch_update_guest_debug()