Lines Matching refs:ri
39 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) in raw_read() argument
41 assert(ri->fieldoffset); in raw_read()
42 if (cpreg_field_is_64bit(ri)) { in raw_read()
43 return CPREG_FIELD64(env, ri); in raw_read()
45 return CPREG_FIELD32(env, ri); in raw_read()
49 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in raw_write() argument
51 assert(ri->fieldoffset); in raw_write()
52 if (cpreg_field_is_64bit(ri)) { in raw_write()
53 CPREG_FIELD64(env, ri) = value; in raw_write()
55 CPREG_FIELD32(env, ri) = value; in raw_write()
59 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) in raw_ptr() argument
61 return (char *)env + ri->fieldoffset; in raw_ptr()
64 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) in read_raw_cp_reg() argument
67 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg()
68 return ri->resetvalue; in read_raw_cp_reg()
69 } else if (ri->raw_readfn) { in read_raw_cp_reg()
70 return ri->raw_readfn(env, ri); in read_raw_cp_reg()
71 } else if (ri->readfn) { in read_raw_cp_reg()
72 return ri->readfn(env, ri); in read_raw_cp_reg()
74 return raw_read(env, ri); in read_raw_cp_reg()
78 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, in write_raw_cp_reg() argument
87 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg()
89 } else if (ri->raw_writefn) { in write_raw_cp_reg()
90 ri->raw_writefn(env, ri, v); in write_raw_cp_reg()
91 } else if (ri->writefn) { in write_raw_cp_reg()
92 ri->writefn(env, ri, v); in write_raw_cp_reg()
94 raw_write(env, ri, v); in write_raw_cp_reg()
98 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) in raw_accessors_invalid() argument
112 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid()
113 ri->fieldoffset || in raw_accessors_invalid()
114 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { in raw_accessors_invalid()
128 const ARMCPRegInfo *ri; in write_cpustate_to_list() local
131 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_cpustate_to_list()
132 if (!ri) { in write_cpustate_to_list()
136 if (ri->type & ARM_CP_NO_RAW) { in write_cpustate_to_list()
140 newval = read_raw_cp_reg(&cpu->env, ri); in write_cpustate_to_list()
154 write_raw_cp_reg(&cpu->env, ri, oldval); in write_cpustate_to_list()
155 if (read_raw_cp_reg(&cpu->env, ri) != oldval) { in write_cpustate_to_list()
159 write_raw_cp_reg(&cpu->env, ri, newval); in write_cpustate_to_list()
174 const ARMCPRegInfo *ri; in write_list_to_cpustate() local
176 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_list_to_cpustate()
177 if (!ri) { in write_list_to_cpustate()
181 if (ri->type & ARM_CP_NO_RAW) { in write_list_to_cpustate()
189 write_raw_cp_reg(&cpu->env, ri, v); in write_list_to_cpustate()
190 if (read_raw_cp_reg(&cpu->env, ri) != v) { in write_list_to_cpustate()
201 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in add_cpreg_to_list() local
203 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in add_cpreg_to_list()
213 const ARMCPRegInfo *ri; in count_cpreg() local
215 ri = g_hash_table_lookup(cpu->cp_regs, key); in count_cpreg()
217 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in count_cpreg()
283 const ARMCPRegInfo *ri, in access_el3_aa32ns() argument
300 const ARMCPRegInfo *ri, in access_trap_aa32s_el1() argument
320 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, in access_tpm() argument
336 CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, in access_tvm_trvm() argument
349 static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, in access_tsw() argument
359 static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, in access_tacr() argument
369 static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlb() argument
379 static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlbis() argument
391 static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlbos() argument
402 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in dacr_write() argument
406 raw_write(env, ri, value); in dacr_write()
410 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in fcse_write() argument
414 if (raw_read(env, ri) != value) { in fcse_write()
420 raw_write(env, ri, value); in fcse_write()
424 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, in contextidr_write() argument
429 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) in contextidr_write()
438 raw_write(env, ri, value); in contextidr_write()
460 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_is_write() argument
468 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiasid_is_write() argument
476 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_is_write() argument
484 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimvaa_is_write() argument
502 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_write() argument
515 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_write() argument
529 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiasid_write() argument
542 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimvaa_write() argument
556 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_nsnh_write() argument
564 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_nsnh_is_write() argument
573 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_hyp_write() argument
581 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_hyp_is_write() argument
589 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_hyp_write() argument
598 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_hyp_is_write() argument
608 static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiipas2_hyp_write() argument
617 static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiipas2is_hyp_write() argument
757 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, in cpacr_write() argument
806 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) in cpacr_read() argument
822 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) in cpacr_reset() argument
828 cpacr_write(env, ri, 0); in cpacr_reset()
831 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, in cpacr_access() argument
849 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, in cptr_access() argument
1090 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, in pmreg_access() argument
1115 const ARMCPRegInfo *ri, in pmreg_access_xevcntr() argument
1126 return pmreg_access(env, ri, isread); in pmreg_access_xevcntr()
1130 const ARMCPRegInfo *ri, in pmreg_access_swinc() argument
1141 return pmreg_access(env, ri, isread); in pmreg_access_swinc()
1145 const ARMCPRegInfo *ri, in pmreg_access_selr() argument
1155 return pmreg_access(env, ri, isread); in pmreg_access_selr()
1159 const ARMCPRegInfo *ri, in pmreg_access_ccntr() argument
1170 return pmreg_access(env, ri, isread); in pmreg_access_ccntr()
1484 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmcr_write() argument
1507 static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmcr_read() argument
1523 static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmswinc_write() argument
1559 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmccntr_read() argument
1568 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmselr_write() argument
1580 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmccntr_write() argument
1588 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, in pmccntr_write32() argument
1593 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); in pmccntr_write32()
1596 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmccfiltr_write() argument
1604 static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, in pmccfiltr_write_a32() argument
1614 static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) in pmccfiltr_read_a32() argument
1620 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmcntenset_write() argument
1629 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmcntenclr_write() argument
1638 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmovsr_write() argument
1646 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmovsset_write() argument
1654 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmevtyper_write() argument
1658 pmccfiltr_write(env, ri, value); in pmevtyper_write()
1690 static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, in pmevtyper_read() argument
1706 static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, in pmevtyper_writefn() argument
1709 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn()
1710 pmevtyper_write(env, ri, value, counter); in pmevtyper_writefn()
1713 static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, in pmevtyper_rawwrite() argument
1716 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite()
1736 static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) in pmevtyper_readfn() argument
1738 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn()
1739 return pmevtyper_read(env, ri, counter); in pmevtyper_readfn()
1742 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmxevtyper_write() argument
1745 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevtyper_write()
1748 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmxevtyper_read() argument
1750 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevtyper_read()
1753 static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmevcntr_write() argument
1771 static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, in pmevcntr_read() argument
1793 static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, in pmevcntr_writefn() argument
1796 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn()
1797 pmevcntr_write(env, ri, value, counter); in pmevcntr_writefn()
1800 static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) in pmevcntr_readfn() argument
1802 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn()
1803 return pmevcntr_read(env, ri, counter); in pmevcntr_readfn()
1806 static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, in pmevcntr_rawwrite() argument
1809 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite()
1812 pmevcntr_write(env, ri, value, counter); in pmevcntr_rawwrite()
1815 static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) in pmevcntr_rawread() argument
1817 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread()
1822 static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmxevcntr_write() argument
1825 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevcntr_write()
1828 static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmxevcntr_read() argument
1830 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevcntr_read()
1833 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmuserenr_write() argument
1843 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmintenset_write() argument
1852 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmintenclr_write() argument
1860 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, in vbar_write() argument
1870 raw_write(env, ri, value & ~0x1FULL); in vbar_write()
1873 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in scr_write() argument
1975 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) in scr_reset() argument
1981 scr_write(env, ri, 0); in scr_reset()
1985 const ARMCPRegInfo *ri, in access_tid4() argument
1996 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ccsidr_read() argument
2005 ri->secure & ARM_CP_SECSTATE_S); in ccsidr_read()
2010 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, in csselr_write() argument
2013 raw_write(env, ri, value & 0xf); in csselr_write()
2016 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) in isr_read() argument
2065 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, in access_aa64_tid1() argument
2075 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, in access_aa32_tid1() argument
2079 return access_aa64_tid1(env, ri, isread); in access_aa32_tid1()
2404 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, in teecr_write() argument
2411 static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, in teecr_access() argument
2425 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, in teehbr_access() argument
2431 return teecr_access(env, ri, isread); in teehbr_access()
2489 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, in gt_cntfrq_access() argument
2513 if (!isread && ri->state == ARM_CP_STATE_AA32 && in gt_cntfrq_access()
2618 const ARMCPRegInfo *ri, in gt_pct_access() argument
2625 const ARMCPRegInfo *ri, in gt_vct_access() argument
2631 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, in gt_ptimer_access() argument
2637 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, in gt_vtimer_access() argument
2644 const ARMCPRegInfo *ri, in gt_stimer_access() argument
2793 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, in gt_timer_reset() argument
2801 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_cnt_read() argument
2828 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_virt_cnt_read() argument
2833 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_cval_write() argument
2842 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, in gt_tval_read() argument
2861 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_tval_write() argument
2883 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_ctl_write() argument
2905 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gt_phys_timer_reset() argument
2907 gt_timer_reset(env, ri, GTIMER_PHYS); in gt_phys_timer_reset()
2910 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_cval_write() argument
2913 gt_cval_write(env, ri, GTIMER_PHYS, value); in gt_phys_cval_write()
2916 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_phys_tval_read() argument
2918 return gt_tval_read(env, ri, GTIMER_PHYS); in gt_phys_tval_read()
2921 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_tval_write() argument
2924 gt_tval_write(env, ri, GTIMER_PHYS, value); in gt_phys_tval_write()
2927 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_ctl_write() argument
2930 gt_ctl_write(env, ri, GTIMER_PHYS, value); in gt_phys_ctl_write()
2958 const ARMCPRegInfo *ri) in gt_phys_redir_cval_read() argument
2964 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_redir_cval_write() argument
2968 gt_cval_write(env, ri, timeridx, value); in gt_phys_redir_cval_write()
2972 const ARMCPRegInfo *ri) in gt_phys_redir_tval_read() argument
2975 return gt_tval_read(env, ri, timeridx); in gt_phys_redir_tval_read()
2978 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_redir_tval_write() argument
2982 gt_tval_write(env, ri, timeridx, value); in gt_phys_redir_tval_write()
2986 const ARMCPRegInfo *ri) in gt_phys_redir_ctl_read() argument
2992 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_phys_redir_ctl_write() argument
2996 gt_ctl_write(env, ri, timeridx, value); in gt_phys_redir_ctl_write()
2999 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gt_virt_timer_reset() argument
3001 gt_timer_reset(env, ri, GTIMER_VIRT); in gt_virt_timer_reset()
3004 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_cval_write() argument
3007 gt_cval_write(env, ri, GTIMER_VIRT, value); in gt_virt_cval_write()
3010 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_virt_tval_read() argument
3012 return gt_tval_read(env, ri, GTIMER_VIRT); in gt_virt_tval_read()
3015 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_tval_write() argument
3018 gt_tval_write(env, ri, GTIMER_VIRT, value); in gt_virt_tval_write()
3021 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_ctl_write() argument
3024 gt_ctl_write(env, ri, GTIMER_VIRT, value); in gt_virt_ctl_write()
3027 static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_cnthctl_write() argument
3061 raw_write(env, ri, value); in gt_cnthctl_write()
3070 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_cntvoff_write() argument
3076 raw_write(env, ri, value); in gt_cntvoff_write()
3081 const ARMCPRegInfo *ri) in gt_virt_redir_cval_read() argument
3087 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_redir_cval_write() argument
3091 gt_cval_write(env, ri, timeridx, value); in gt_virt_redir_cval_write()
3095 const ARMCPRegInfo *ri) in gt_virt_redir_tval_read() argument
3098 return gt_tval_read(env, ri, timeridx); in gt_virt_redir_tval_read()
3101 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_redir_tval_write() argument
3105 gt_tval_write(env, ri, timeridx, value); in gt_virt_redir_tval_write()
3109 const ARMCPRegInfo *ri) in gt_virt_redir_ctl_read() argument
3115 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_virt_redir_ctl_write() argument
3119 gt_ctl_write(env, ri, timeridx, value); in gt_virt_redir_ctl_write()
3122 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gt_hyp_timer_reset() argument
3124 gt_timer_reset(env, ri, GTIMER_HYP); in gt_hyp_timer_reset()
3127 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hyp_cval_write() argument
3130 gt_cval_write(env, ri, GTIMER_HYP, value); in gt_hyp_cval_write()
3133 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_hyp_tval_read() argument
3135 return gt_tval_read(env, ri, GTIMER_HYP); in gt_hyp_tval_read()
3138 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hyp_tval_write() argument
3141 gt_tval_write(env, ri, GTIMER_HYP, value); in gt_hyp_tval_write()
3144 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hyp_ctl_write() argument
3147 gt_ctl_write(env, ri, GTIMER_HYP, value); in gt_hyp_ctl_write()
3150 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gt_sec_timer_reset() argument
3152 gt_timer_reset(env, ri, GTIMER_SEC); in gt_sec_timer_reset()
3155 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_sec_cval_write() argument
3158 gt_cval_write(env, ri, GTIMER_SEC, value); in gt_sec_cval_write()
3161 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_sec_tval_read() argument
3163 return gt_tval_read(env, ri, GTIMER_SEC); in gt_sec_tval_read()
3166 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_sec_tval_write() argument
3169 gt_tval_write(env, ri, GTIMER_SEC, value); in gt_sec_tval_write()
3172 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_sec_ctl_write() argument
3175 gt_ctl_write(env, ri, GTIMER_SEC, value); in gt_sec_ctl_write()
3178 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gt_hv_timer_reset() argument
3180 gt_timer_reset(env, ri, GTIMER_HYPVIRT); in gt_hv_timer_reset()
3183 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hv_cval_write() argument
3186 gt_cval_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_cval_write()
3189 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_hv_tval_read() argument
3191 return gt_tval_read(env, ri, GTIMER_HYPVIRT); in gt_hv_tval_read()
3194 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hv_tval_write() argument
3197 gt_tval_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_tval_write()
3200 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_hv_ctl_write() argument
3203 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_ctl_write()
3468 const ARMCPRegInfo *ri, in gt_cntpoff_access() argument
3478 static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri, in gt_cntpoff_write() argument
3484 raw_write(env, ri, value); in gt_cntpoff_write()
3503 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) in gt_virt_cnt_read() argument
3543 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in par_write() argument
3546 raw_write(env, ri, value); in par_write()
3548 raw_write(env, ri, value & 0xfffff6ff); in par_write()
3550 raw_write(env, ri, value & 0xfffff1ff); in par_write()
3557 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, in ats_access() argument
3560 if (ri->opc2 & 4) { in ats_access()
3768 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in ats_write() argument
3771 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write()
3777 switch (ri->opc2 & 6) { in ats_write()
3782 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3792 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3842 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, in ats1h_write() argument
3846 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats1h_write()
3860 static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, in at_e012_access() argument
3876 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, in at_s1e2_access() argument
3883 return at_e012_access(env, ri, isread); in at_s1e2_access()
3886 static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo *ri, in at_s1e01_access() argument
3892 return at_e012_access(env, ri, isread); in at_s1e01_access()
3895 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, in ats_write64() argument
3899 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write64()
3906 switch (ri->opc2 & 6) { in ats_write64()
3908 switch (ri->opc1) { in ats_write64()
3910 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write64()
3980 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmsav5_data_ap_write() argument
3986 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmsav5_data_ap_read() argument
3991 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmsav5_insn_ap_write() argument
3997 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmsav5_insn_ap_read() argument
4002 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmsav7_read() argument
4004 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); in pmsav7_read()
4014 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmsav7_write() argument
4018 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); in pmsav7_write()
4029 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmsav7_rgnr_write() argument
4042 raw_write(env, ri, value); in pmsav7_rgnr_write()
4045 static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, in prbar_write() argument
4054 static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) in prbar_read() argument
4059 static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, in prlar_write() argument
4068 static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) in prlar_read() argument
4073 static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, in prselr_write() argument
4089 static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, in hprbar_write() argument
4098 static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) in hprbar_read() argument
4103 static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, in hprlar_write() argument
4112 static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) in hprlar_read() argument
4117 static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, in hprenr_write() argument
4138 static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) in hprenr_read() argument
4153 static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, in hprselr_write() argument
4169 static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, in pmsav8r_regn_write() argument
4173 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_write()
4174 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_write()
4178 if (ri->opc1 & 4) { in pmsav8r_regn_write()
4182 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4191 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4199 static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) in pmsav8r_regn_read() argument
4202 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_read()
4203 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_read()
4205 if (ri->opc1 & 4) { in pmsav8r_regn_read()
4209 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4218 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4339 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in vmsa_ttbcr_write() argument
4370 raw_write(env, ri, value); in vmsa_ttbcr_write()
4373 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, in vmsa_tcr_el12_write() argument
4380 raw_write(env, ri, value); in vmsa_tcr_el12_write()
4383 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, in vmsa_ttbr_write() argument
4387 if (cpreg_field_is_64bit(ri) && in vmsa_ttbr_write()
4388 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { in vmsa_ttbr_write()
4392 raw_write(env, ri, value); in vmsa_ttbr_write()
4395 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, in vmsa_tcr_ttbr_el2_write() argument
4404 if (extract64(raw_read(env, ri) ^ value, 48, 16) && in vmsa_tcr_ttbr_el2_write()
4411 raw_write(env, ri, value); in vmsa_tcr_ttbr_el2_write()
4414 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, in vttbr_write() argument
4424 if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { in vttbr_write()
4427 raw_write(env, ri, value); in vttbr_write()
4506 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, in omap_ticonfig_write() argument
4515 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, in omap_threadid_write() argument
4521 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, in omap_wfi_write() argument
4528 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, in omap_cachemaint_write() argument
4579 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, in xscale_cpar_write() argument
4674 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) in midr_read() argument
4681 return raw_read(env, ri); in midr_read()
4703 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) in mpidr_read() argument
4743 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_fpcr_read() argument
4748 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_fpcr_write() argument
4754 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_fpsr_read() argument
4759 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_fpsr_write() argument
4765 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_daif_access() argument
4774 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_daif_write() argument
4780 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_pan_read() argument
4785 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_pan_write() argument
4798 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_uao_read() argument
4803 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_uao_write() argument
4816 static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_dit_read() argument
4821 static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_dit_write() argument
4834 static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_ssbs_read() argument
4839 static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_ssbs_write() argument
4853 const ARMCPRegInfo *ri, in aa64_cacheop_poc_access() argument
4894 static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, in access_ticab() argument
4900 static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, in access_tocu() argument
4993 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vmalle1is_write() argument
5002 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vmalle1_write() argument
5023 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle1_write() argument
5032 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle2_write() argument
5041 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle3_write() argument
5050 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle1is_write() argument
5059 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle2is_write() argument
5068 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_alle3is_write() argument
5076 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae2_write() argument
5092 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae3_write() argument
5107 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae1is_write() argument
5118 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae1_write() argument
5139 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae2is_write() argument
5150 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_vae3is_write() argument
5174 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_ipas2e1_write() argument
5188 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_ipas2e1is_write() argument
5290 const ARMCPRegInfo *ri, in tlbi_aa64_rvae1_write() argument
5305 const ARMCPRegInfo *ri, in tlbi_aa64_rvae1is_write() argument
5320 const ARMCPRegInfo *ri, in tlbi_aa64_rvae2_write() argument
5337 const ARMCPRegInfo *ri, in tlbi_aa64_rvae2is_write() argument
5352 const ARMCPRegInfo *ri, in tlbi_aa64_rvae3_write() argument
5366 const ARMCPRegInfo *ri, in tlbi_aa64_rvae3is_write() argument
5379 static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_ripas2e1_write() argument
5387 const ARMCPRegInfo *ri, in tlbi_aa64_ripas2e1is_write() argument
5394 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_zva_access() argument
5422 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_dczid_read() argument
5434 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, in sp_el0_access() argument
5447 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) in spsel_read() argument
5452 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) in spsel_write() argument
5457 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, in sctlr_write() argument
5469 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { in sctlr_write()
5470 if (ri->opc1 == 6) { /* SCTLR_EL3 */ in sctlr_write()
5478 if (raw_read(env, ri) == value) { in sctlr_write()
5486 raw_write(env, ri, value); in sctlr_write()
5491 if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { in sctlr_write()
5502 static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, in mdcr_el3_write() argument
5521 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in sdcr_write() argument
5525 mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); in sdcr_write()
5528 static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, in mdcr_el2_write() argument
5547 static CPAccessResult access_nv1(CPUARMState *env, const ARMCPRegInfo *ri, in access_nv1() argument
5570 static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, in ic_ivau_write() argument
6090 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in hcr_write() argument
6095 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, in hcr_writehigh() argument
6103 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, in hcr_writelow() argument
6217 static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, in hcrx_write() argument
6259 static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, in access_hxen() argument
6307 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, in cptr_el2_write() argument
6322 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) in cptr_el2_read() argument
6596 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, in sel2_access() argument
6618 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, in nsacr_access() argument
6742 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, in e2h_access() argument
6755 static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri, in access_el1nvpct() argument
6764 return e2h_access(env, ri, isread); in access_el1nvpct()
6767 static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri, in access_el1nvvct() argument
6776 return e2h_access(env, ri, isread); in access_el1nvvct()
6785 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) in el2_e2h_read() argument
6791 ri = ri->opaque; in el2_e2h_read()
6792 readfn = ri->readfn; in el2_e2h_read()
6794 readfn = ri->orig_readfn; in el2_e2h_read()
6799 return readfn(env, ri); in el2_e2h_read()
6802 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, in el2_e2h_write() argument
6809 ri = ri->opaque; in el2_e2h_write()
6810 writefn = ri->writefn; in el2_e2h_write()
6812 writefn = ri->orig_writefn; in el2_e2h_write()
6817 writefn(env, ri, value); in el2_e2h_write()
6820 static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) in el2_e2h_e12_read() argument
6823 return ri->orig_readfn(env, ri->opaque); in el2_e2h_e12_read()
6826 static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, in el2_e2h_e12_write() argument
6830 return ri->orig_writefn(env, ri->opaque, value); in el2_e2h_e12_write()
6834 const ARMCPRegInfo *ri, in el2_e2h_e12_access() argument
6850 if (ri->orig_accessfn) { in el2_e2h_e12_access()
6851 return ri->orig_accessfn(env, ri->opaque, isread); in el2_e2h_e12_access()
7010 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, in ctr_el0_access() argument
7047 static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, in access_terr() argument
7061 static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) in disr_read() argument
7074 static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) in disr_write() argument
7275 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in zcr_write() argument
7284 raw_write(env, ri, value & 0xf); in zcr_write()
7316 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, in access_tpidr2() argument
7336 static CPAccessResult access_smprimap(CPUARMState *env, const ARMCPRegInfo *ri, in access_smprimap() argument
7348 static CPAccessResult access_smpri(CPUARMState *env, const ARMCPRegInfo *ri, in access_smpri() argument
7398 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in svcr_write() argument
7404 static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in smcr_write() argument
7413 raw_write(env, ri, value); in smcr_write()
7480 static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_paall_write() argument
7488 static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, in gpccr_write() argument
7499 static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) in gpccr_reset() argument
7505 static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbi_aa64_paallos_write() argument
7557 static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, in aa64_allint_write() argument
7563 static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri) in aa64_allint_read() argument
7569 const ARMCPRegInfo *ri, bool isread) in aa64_allint_access() argument
7695 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) in id_pfr1_read() argument
7706 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) in id_aa64pfr0_read() argument
7723 const ARMCPRegInfo *ri, bool isread) in access_lor_ns() argument
7737 const ARMCPRegInfo *ri, bool isread) in access_lor_other() argument
7743 return access_lor_ns(env, ri, isread); in access_lor_other()
7780 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, in access_pauth() argument
8055 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) in rndr_readfn() argument
8072 ri->name, error_get_pretty(err)); in rndr_readfn()
8143 static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, in access_aa64_tid5() argument
8153 static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, in access_mte() argument
8171 static CPAccessResult access_tfsr_el1(CPUARMState *env, const ARMCPRegInfo *ri, in access_tfsr_el1() argument
8174 CPAccessResult nv1 = access_nv1(env, ri, isread); in access_tfsr_el1()
8179 return access_mte(env, ri, isread); in access_tfsr_el1()
8182 static CPAccessResult access_tfsr_el2(CPUARMState *env, const ARMCPRegInfo *ri, in access_tfsr_el2() argument
8211 static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) in tco_read() argument
8216 static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) in tco_write() argument
8355 static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, in access_scxtnum() argument
8383 const ARMCPRegInfo *ri, in access_scxtnum_el1() argument
8386 CPAccessResult nv1 = access_nv1(env, ri, isread); in access_scxtnum_el1()
8391 return access_scxtnum(env, ri, isread); in access_scxtnum_el1()
8416 static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, in access_fgt() argument
8454 static void vncr_write(CPUARMState *env, const ARMCPRegInfo *ri, in vncr_write() argument
8478 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, in access_predinv() argument
8527 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) in ccsidr2_read() argument
8530 return extract64(ccsidr_read(env, ri), 32, 32); in ccsidr2_read()
8541 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, in access_aa64_tid3() argument
8551 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, in access_aa32_tid3() argument
8555 return access_aa64_tid3(env, ri, isread); in access_aa32_tid3()
8561 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, in access_jazelle() argument
8572 const ARMCPRegInfo *ri, bool isread) in access_joscr_jmcr() argument
10419 for (size_t ri = 0; ri < regs_len; ++ri) { in modify_arm_cp_regs_with_len() local
10420 ARMCPRegInfo *r = regs + ri; in modify_arm_cp_regs_with_len()
10446 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, in arm_cp_write_ignore() argument
10452 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) in arm_cp_read_zero() argument