Lines Matching +full:mixed +full:- +full:signals
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
80 /* ARM-specific interrupt pending bits. */
103 /* ARM-specific extra insn start words:
114 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
149 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
150 * For 64-bit, this is a 2048-bit SVE register.
211 * FPST_A32_F16: used for AArch32 half-precision calculations
212 * FPST_A64_F16: used for AArch64 half-precision calculations
214 * FPST_STD_F16: used for half-precision
222 * for half-precision
224 * Half-precision operations are governed by a separate
225 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
228 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
229 * round-to-nearest and is used by any operations (generally
277 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
279 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
280 * DAIF (exception masks) are kept in env->daif
281 * BTYPE is kept in env->btype
282 * SM and ZA are kept in env->svcr
283 * all other bits are stored in their correct places in env->pstate
303 /* These hold r8-r12. */
348 uint32_t nsacr; /* Non-secure access control register. */
519 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
520 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
521 uint32_t c15_threadid; /* TI debugger thread-ID. */
539 * architecturally-correct value is being read/set.
566 * Fine-Grained Trap registers. We store these as arrays so the
587 * of the Secure and Non-Secure states. (If the CPU doesn't support
590 * and the non-active SP for the current security state in
630 * code which raises an exception must set cs->exception_index and
632 * will then set the guest-visible registers as part of the exception
657 /* Thumb-2 EE state. */
693 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
694 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
700 * Contains the 'val' for the second 64-bit register of LDXP, which comes
701 * from the higher address, not the high part of a complete 128-bit value.
728 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
730 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
814 env->features |= 1ULL << feature; in set_feature()
819 env->features &= ~(1ULL << feature); in unset_feature()
846 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
900 * pmu_op_finish() - it does not need other handling during migration
947 /* CPU has M-profile DSP extension */
962 * 0 - disabled, 1 - smc, 2 - hvc
968 /* For v8M, initial value of the Non-secure VTOR */
999 /* QOM property to indicate we should use the back-compat CNTFRQ default */
1002 /* QOM property to indicate we should use the back-compat QARMA5 default */
1010 /* The instance init functions for implementation-specific subclasses
1011 * set these fields to specify the implementation-dependent values of
1012 * various constant registers and reset values of non-constant
1017 * is used for reset values of non-constant registers; no reset_
1023 * you need to also update the 32-bit and 64-bit versions of the
1103 uint64_t rvbar_prop; /* Property/input signals. */
1112 * big-endian mode). This setting isn't used directly: instead it modifies
1123 /* Used to synchronize KVM and QEMU in-kernel device levels */
1227 * lower exception level. This function does that post-reset CPU setup,
1248 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1249 * The byte at offset i from the start of the in-memory representation contains
1252 * matches QEMU's representation, which is to use an array of host-endian
1254 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1292 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1302 return env->aarch64; in is_a64()
1310 * they are enabled) and the guest-visible values. These two calls must
1346 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1349 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1363 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1365 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1384 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1386 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1388 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1397 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1399 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1406 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1407 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1408 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1409 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1410 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1411 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1412 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1479 * AArch32 mode SPSRs are basically CPSR-format.
1532 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1540 ZF = (env->ZF == 0); in pstate_read()
1541 return (env->NF & 0x80000000) | (ZF << 30) in pstate_read()
1542 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) in pstate_read()
1543 | env->pstate | env->daif | (env->btype << 10); in pstate_read()
1548 env->ZF = (~val) & PSTATE_Z; in pstate_write()
1549 env->NF = val; in pstate_write()
1550 env->CF = (val >> 29) & 1; in pstate_write()
1551 env->VF = (val << 3) & 0x80000000; in pstate_write()
1552 env->daif = val & PSTATE_DAIF; in pstate_write()
1553 env->btype = (val >> 10) & 3; in pstate_write()
1554 env->pstate = val & ~CACHED_PSTATE_BITS; in pstate_write()
1569 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1581 ZF = (env->ZF == 0); in xpsr_read()
1582 return (env->NF & 0x80000000) | (ZF << 30) in xpsr_read()
1583 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in xpsr_read()
1584 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1585 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1586 | (env->GE << 16) in xpsr_read()
1587 | env->v7m.exception; in xpsr_read()
1590 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1594 env->ZF = (~val) & XPSR_Z; in xpsr_write()
1595 env->NF = val; in xpsr_write()
1596 env->CF = (val >> 29) & 1; in xpsr_write()
1597 env->VF = (val << 3) & 0x80000000; in xpsr_write()
1600 env->QF = ((val & XPSR_Q) != 0); in xpsr_write()
1603 env->GE = (val & XPSR_GE) >> 16; in xpsr_write()
1607 env->thumb = ((val & XPSR_T) != 0); in xpsr_write()
1610 env->condexec_bits &= ~3; in xpsr_write()
1611 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1614 env->condexec_bits &= 3; in xpsr_write()
1615 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1752 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1753 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1756 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1758 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1760 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1846 /* These ones are M-profile only */
1853 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1964 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1989 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2401 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2402 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2403 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2404 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2405 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2406 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2426 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2429 * HWCAP bit, remember to update the feature-bit-to-hwcap
2430 * mapping in linux-user/elfload.c:get_elf_hwcap().
2446 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2454 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2462 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2483 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2501 /* Return true if @space is secure, in the pre-v9 sense. */
2507 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2542 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { in arm_is_el3_or_mon()
2546 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2582 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate()
2640 * access the secure or non-secure bank of a cp register. When EL3 is
2641 * operating in AArch32 state, the NS-bit determines whether the secure
2644 * accesses are to the non-secure version.
2666 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2680 * Note that we do not stop early on failure -- we will attempt
2697 * values in the list if the previous list->cpustate sync actually
2703 * Note that we do not stop early on failure -- we will attempt
2713 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2717 * If EL3 is 64-bit:
2721 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2730 * If EL3 is 32-bit:
2739 * because they may differ in access permissions even if the VA->PA map is
2741 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2748 * which can be slow-pathed and always do a page table walk.
2760 * 7. we fold together most secure and non-secure regimes for A-profile,
2762 * process of switching between secure and non-secure is
2787 * EL2 for cores like the Cortex-R52).
2802 * are not quite the same -- different CPU types (most notably M profile
2837 * A-profile.
2859 /* TLBs with 1-1 mapping to the physical address spaces. */
2874 * M-profile.
2887 * Bit macros for the core-mmu-index values for each index,
2943 return idx - ARMMMUIdx_Phys_S; in arm_phys_to_space()
2951 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
2957 /* We need not implement SCTLR.ITD in user-mode emulation, so in arm_sctlr_b()
2958 * let linux-user ignore the fact that it conflicts with SCTLR_B. in arm_sctlr_b()
2959 * This lets people run BE32 binaries with "-cpu any". in arm_sctlr_b()
2964 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
2969 #include "exec/cpu-all.h"
2972 * We have more than 32-bits worth of state per TB, so we split the data
2973 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2980 * address size, flags2 always has 64-bits for A64, and a minimum of
2981 * 32-bits for A32 and M32.
2983 * The bits for 32-bit A-profile and M-profile partially overlap:
2986 * +-------------+----------+----------------+
2988 * | TBFLAG_AM32 | +-----+----------+
2990 * +-------------+----------------+----------+
2993 * Unless otherwise noted, these bits are cached in env->hflags.
3000 /* Target EL if we take a floating-point-disabled exception */
3009 * Bit usage when in AArch32 state, both A- and M-profile.
3015 * Bit usage when in AArch32 state, for A-profile only.
3042 * Bit usage when in AArch32 state, for M-profile only.
3046 /* Whether we should generate stack-limit checks */
3089 /* Set if FEAT_NV2 RAM accesses are big-endian */
3120 * Return the VL cached within env->hflags, in units of quadwords.
3124 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3131 * Return the SVL cached within env->hflags, in units of quadwords.
3135 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3141 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. in bswap_code()
3143 * would also end up as a mixed-endian mode with BE code, LE data. in bswap_code()
3187 * Note that if a pre-change hook is called, any registered post-change hooks
3200 * if pre-change hooks have been.
3213 * Return a pointer to the Dn register within env in 32-bit mode.
3217 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3222 * Return a pointer to the Qn register within env in 32-bit mode.
3226 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg()
3231 * Return a pointer to the Qn register within env in 64-bit mode.
3235 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
3238 /* Shared between translate-sve.c and sve_helper.c. */
3242 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3268 * include/exec/cpu_ldst.h, and not some place linux-user specific.
3273 if (env->tagged_addr_enable) { in cpu_untagged_addr()