qemu/system/memory_ldst.c.inc

29     MemoryRegion *mr;
36     mr = TRANSLATE(addr, &addr1, &l, false, attrs);
37     if (l < 4 || !memory_access_is_direct(mr, false, attrs)) {
38         release_lock |= prepare_mmio_access(mr);
41         r = memory_region_dispatch_read(mr, addr1, &val,
45         fuzz_dma_read_cb(addr, 4, mr);
46         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
98     MemoryRegion *mr;
105     mr = TRANSLATE(addr, &addr1, &l, false, attrs);
106     if (l < 8 || !memory_access_is_direct(mr, false, attrs)) {
107         release_lock |= prepare_mmio_access(mr);
110         r = memory_region_dispatch_read(mr, addr1, &val,
114         fuzz_dma_read_cb(addr, 8, mr);
115         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
165     MemoryRegion *mr;
172     mr = TRANSLATE(addr, &addr1, &l, false, attrs);
173     if (!memory_access_is_direct(mr, false, attrs)) {
174         release_lock |= prepare_mmio_access(mr);
177         r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
180         fuzz_dma_read_cb(addr, 1, mr);
181         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
202     MemoryRegion *mr;
209     mr = TRANSLATE(addr, &addr1, &l, false, attrs);
210     if (l < 2 || !memory_access_is_direct(mr, false, attrs)) {
211         release_lock |= prepare_mmio_access(mr);
214         r = memory_region_dispatch_read(mr, addr1, &val,
218         fuzz_dma_read_cb(addr, 2, mr);
219         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
271     MemoryRegion *mr;
279     mr = TRANSLATE(addr, &addr1, &l, true, attrs);
280     if (l < 4 || !memory_access_is_direct(mr, true, attrs)) {
281         release_lock |= prepare_mmio_access(mr);
283         r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
285         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
288         dirty_log_mask = memory_region_get_dirty_log_mask(mr);
290         cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
309     MemoryRegion *mr;
316     mr = TRANSLATE(addr, &addr1, &l, true, attrs);
317     if (l < 4 || !memory_access_is_direct(mr, true, attrs)) {
318         release_lock |= prepare_mmio_access(mr);
319         r = memory_region_dispatch_write(mr, addr1, val,
323         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
335         invalidate_and_set_dirty(mr, addr1, 4);
372     MemoryRegion *mr;
379     mr = TRANSLATE(addr, &addr1, &l, true, attrs);
380     if (!memory_access_is_direct(mr, true, attrs)) {
381         release_lock |= prepare_mmio_access(mr);
382         r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);
385         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
387         invalidate_and_set_dirty(mr, addr1, 1);
405     MemoryRegion *mr;
412     mr = TRANSLATE(addr, &addr1, &l, true, attrs);
413     if (l < 2 || !memory_access_is_direct(mr, true, attrs)) {
414         release_lock |= prepare_mmio_access(mr);
415         r = memory_region_dispatch_write(mr, addr1, val,
419         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
431         invalidate_and_set_dirty(mr, addr1, 2);
469     MemoryRegion *mr;
476     mr = TRANSLATE(addr, &addr1, &l, true, attrs);
477     if (l < 8 || !memory_access_is_direct(mr, true, attrs)) {
478         release_lock |= prepare_mmio_access(mr);
479         r = memory_region_dispatch_write(mr, addr1, val,
483         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
495         invalidate_and_set_dirty(mr, addr1, 8);