Lines Matching +full:interrupt +full:- +full:counter
3 // SPDX-License-Identifier: GPL-2.0-or-later
56 /// Counter Size (bit 13)
63 /// Main Counter Tick Period (bits 32:63)
74 /// bit 4, 5, 15, and bits 32:64 are read-only.
76 /// Timer N Interrupt Type (bit 1)
78 /// Timer N Interrupt Enable (bit 2)
82 /// Timer N Periodic Interrupt Capable (support Periodic or not, bit 4)
84 /// Timer N Size (timer size is 64-bits or 32 bits, bit 5)
88 /// Timer N 32-bit Mode (bit 8)
90 /// Timer N Interrupt Rout (bits 9:13)
93 /// Timer N FSB Interrupt Enable (bit 14)
95 /// Timer N FSB Interrupt Delivery (bit 15)
97 /// Timer N Interrupt Routing Capability (bits 32:63)
109 /// Timer N FSB Interrupt Route Register
122 /// General Interrupt Status Register
124 /// Main Counter Value Register
125 COUNTER = 0xF0, enumerator
146 const fn hpet_next_wrap(cur_tick: u64) -> u64 { in hpet_next_wrap()
150 const fn hpet_time_after(a: u64, b: u64) -> bool { in hpet_time_after()
151 ((b - a) as i64) < 0 in hpet_time_after()
154 const fn ticks_to_ns(value: u64) -> u64 { in ticks_to_ns()
158 const fn ns_to_ticks(value: u64) -> u64 { in ns_to_ticks()
163 const fn hpet_fixup_reg(new: u64, old: u64, mask: u64) -> u64 { in hpet_fixup_reg()
167 const fn activating_bit(old: u64, new: u64, shift: usize) -> bool { in activating_bit()
172 const fn deactivating_bit(old: u64, new: u64, shift: usize) -> bool { in deactivating_bit()
192 // Memory-mapped, software visible timer registers
197 /// Timer N FSB Interrupt Route Register
201 /// comparator (extended to counter width)
205 /// timer pop will indicate wrap for one-shot 32-bit
242 fn get_state(&self) -> &HPETState { in get_state()
248 fn is_int_active(&self) -> bool { in is_int_active()
252 const fn is_fsb_route_enabled(&self) -> bool { in is_fsb_route_enabled()
256 const fn is_periodic(&self) -> bool { in is_periodic()
260 const fn is_int_enabled(&self) -> bool { in is_int_enabled()
264 const fn is_32bit_mod(&self) -> bool { in is_32bit_mod()
268 const fn is_valset_enabled(&self) -> bool { in is_valset_enabled()
276 /// True if timer interrupt is level triggered; otherwise, edge triggered.
277 const fn is_int_level_triggered(&self) -> bool { in is_int_level_triggered()
281 /// calculate next value of the general counter that matches the
282 /// target (either entirely, or the low 32-bit only depending on
284 fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 { in calculate_cmp64()
296 const fn get_individual_route(&self) -> usize { in get_individual_route()
300 fn get_int_route(&self) -> usize { in get_int_route()
303 // timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, in get_int_route()
304 // timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. in get_int_route()
316 // (If the LegacyReplacement Route bit is set) Timer 2-n will be in get_int_route()
352 // If Timer N Interrupt Enable bit is 0, "the timer will in update_irq()
354 // will not cause an interrupt" in update_irq()
364 if self.is_periodic() && ns - self.last < 1000 { in arm_timer()
378 // HPET spec says in one-shot 32-bit mode, generate an interrupt when in set_timer()
379 // counter wraps in addition to an interrupt with comparator match. in set_timer()
395 // For level-triggered interrupt, this leaves interrupt status in del_timer()
403 // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4) in set_tn_cfg_reg()
408 // Switch level-type interrupt to edge-type. in set_tn_cfg_reg()
436 // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4) in set_tn_cmp_reg()
438 // High 32-bits are zero, leave them untouched. in set_tn_cmp_reg()
440 // TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp() in set_tn_cmp_reg()
461 /// FSB Interrupt Route Register
502 const fn read(&self, reg: TimerRegister) -> u64 { in read()
505 CFG => self.config, // including interrupt capabilities in read()
528 // HPET block Registers: Memory-mapped, software visible registers
533 /// General Interrupt Status Register
536 /// Main Counter Value Register
538 counter: BqlCell<u64>, field
545 /// Offset of main counter relative to qemu clock.
553 /// Interrupt Routing Capability.
555 /// the timers' interrupt can be routed, and is encoded in the
570 const fn has_msi_flag(&self) -> bool { in has_msi_flag()
574 fn is_legacy_mode(&self) -> bool { in is_legacy_mode()
578 fn is_hpet_enabled(&self) -> bool { in is_hpet_enabled()
582 fn is_timer_int_active(&self, index: usize) -> bool { in is_timer_int_active()
586 fn get_ticks(&self) -> u64 { in get_ticks()
590 fn get_ns(&self, tick: u64) -> u64 { in get_ns()
591 ticks_to_ns(tick) - self.hpet_offset.get() in get_ns()
627 // Enable main counter and interrupt generation. in set_cfg_reg()
629 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns()); in set_cfg_reg()
640 // Halt main counter and disable interrupt generation. in set_cfg_reg()
641 self.counter.set(self.get_ticks()); in set_cfg_reg()
654 // TODO: Add irq binding: qemu_irq_lower(s->irqs[0]) in set_cfg_reg()
661 /// General Interrupt Status Register: Read/Write Clear
673 /// Main Counter Value Register
676 // TODO: Add trace point - in set_counter_reg()
680 // done while the counter is halted. So this is an undefined in set_counter_reg()
682 // enabled, the changed counter value will not affect the in set_counter_reg()
686 self.counter in set_counter_reg()
687 .set(self.counter.get().deposit(shift, len, val)); in set_counter_reg()
722 println!("Hpet's hpet-intcap property not initialized"); in realize()
734 // 64-bit General Capabilities and ID Register; LegacyReplacementRoute. in realize()
740 … ((self.num_timers.get() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer in realize()
753 self.counter.set(0); in reset_hold()
768 fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode { in decode()
770 let len = std::cmp::min(size * 8, 64 - shift); in decode()
776 let timer_id: usize = ((addr - 0x100) / 0x20) as usize; in decode()
778 // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id) in decode()
782 // TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id) in decode()
793 fn read(&self, addr: hwaddr, size: u32) -> u64 { in read()
794 // TODO: Add trace point - trace_hpet_ram_read(addr) in read()
804 Global(COUNTER) => { in read()
810 self.counter.get() in read()
814 // TODO: Add trace point- trace_hpet_ram_read_invalid() in read()
823 // TODO: Add trace point - trace_hpet_ram_write(addr, value) in write()
831 Global(COUNTER) => self.set_counter_reg(shift, len, value), in write()
833 // TODO: Add trace point - trace_hpet_ram_write_invalid() in write()
855 // TODO: Make these properties user-configurable!
876 c_str!("hpet-intcap"),
884 c_str!("hpet-offset-saved"),
894 fn properties() -> &'static [Property] { in properties()