pl011/src/registers.rs

3 // SPDX-License-Identifier: GPL-2.0-or-later
14 /// ARM DDI 0183G, Table 3-1 p.3-3
39     /// `IrDA` Low-Power Counter Register
97 /// - if the FIFOs are enabled, data written to this location is pushed onto the
100 /// - if the FIFOs are not enabled, data is stored in the transmitter holding
105 /// prefixed with a start bit, appended with the appropriate parity bit
106 /// (if parity is enabled), and a stop bit. The resultant word is then
111 /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
112 ///   frame, parity,
113 /// and overrun) is pushed onto the 12-bit wide receive FIFO
114 /// - if the FIFOs are not enabled, the data byte and status are stored in the
143     // bilge is not very const-friendly, unfortunately
153 /// information for break, framing and parity corresponds to the
191     fn default() -> Self {  in default()
217     /// becomes non-empty, regardless of whether the UART is enabled
259     fn default() -> Self {  in default()
275     /// If this bit is set to `1`, a low-level is continually output on the
281     /// 1 PEN Parity enable:
283     /// - 0 = parity is disabled and no parity bit added to the data frame
284     /// - 1 = parity checking and generation is enabled.
286     /// See Table 3-11 on page 3-14 for the parity truth table.
288     /// EPS Even parity select. Controls the type of parity the UART uses
290     /// - 0 = odd parity. The UART generates or checks for an odd number of 1s
291     ///   in the data and parity bits.
292     /// - 1 = even parity. The UART generates or checks for an even number of 1s
293     ///   in the data and parity bits.
294     /// This bit has no effect when the `PEN` bit disables parity checking
295     /// and generation. See Table 3-11 on page 3-14 for the parity
297     pub parity: Parity,  field
304     /// 1-byte-deep holding registers 1 = transmit and receive FIFO
313     /// 7 SPS Stick parity select.
314     /// 0 = stick parity is disabled
316     /// • if the EPS bit is 0 then the parity bit is transmitted and checked
317     /// as a 1 • if the EPS bit is 1 then the parity bit is
319     /// the PEN bit disables parity checking and generation. See Table 3-11
320     /// on page 3-14 for the parity truth table.
322     /// 31:8 - Reserved, do not modify, read as zero.
335     fn default() -> Self {  in default()
342 /// `EPS` "Even parity select", field of [Line Control
344 pub enum Parity {  enum
345     /// - 0 = odd parity. The UART generates or checks for an odd number of 1s
346     ///   in the data and parity bits.
347     Odd = 0,  enumerator
348     /// - 1 = even parity. The UART generates or checks for an even number of 1s
349     ///   in the data and parity bits.
359     /// 1-byte-deep holding registers
388 /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
407     /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
408     /// mode. If this bit is cleared to 0, low-level bits are transmitted as
410     /// this bit is set to 1, low-level bits are transmitted with a pulse
419     /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
421     /// be set to 1 to override the normal half-duplex SIR operation. This
467     /// 31:16 - Reserved, do not modify, read as zero.
481     fn default() -> Self {  in default()