3 // SPDX-License-Identifier: GPL-2.0-or-later
6 //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
14 /// ARM DDI 0183G, Table 3-1 p.3-3
20     /// Data Register
22     /// A write to this register initiates the actual data transmission
39     /// `IrDA` Low-Power Counter Register
47     /// line control register (data frame format)
75 /// Receive Status Register / Data Register common error bits
91 /// Data Register, `UARTDR`
93 /// The `UARTDR` register is the data register.
97 /// - if the FIFOs are enabled, data written to this location is pushed onto the
100 /// - if the FIFOs are not enabled, data is stored in the transmitter holding
104 /// The write operation initiates transmission from the UART. The data is
111 /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
113 /// and overrun) is pushed onto the 12-bit wide receive FIFO
114 /// - if the FIFOs are not enabled, the data byte and status are stored in the
118 /// The received data byte is read by performing reads from the `UARTDR`
131 /// ARM DDI 0183G 3.3.1 Data Register, UARTDR
135 pub struct Data {  struct
136     pub data: u8,  field
140 impl_vmstate_bitsized!(Data);  argument
142 impl Data {  implementation
143     // bilge is not very const-friendly, unfortunately
154 /// data character read from the [Data register](Data), `UARTDR` prior to
160 /// The received data character must be read first from the [Data
161 /// Register](Data), `UARTDR` before reading the error status associated
162 /// with that data character from the `UARTRSR` register. This read
180     pub fn set_from_data(&mut self, data: Data) {  in set_from_data()  argument
181         self.set_errors(data.errors());  in set_from_data()
185         // All the bits are cleared to 0 on reset.  in reset()
191     fn default() -> Self {  in default()
205     /// DSR Data set ready. This bit is the complement of the UART data set
209     /// DCD Data carrier detect. This bit is the complement of the UART data
214     /// transmitting data. This bit remains set until the complete
215     /// byte, including all the stop bits, has been sent from the
217     /// becomes non-empty, regardless of whether the UART is enabled
243     /// bit does not indicate if there is data in the transmit shift
259     fn default() -> Self {  in default()
275     /// If this bit is set to `1`, a low-level is continually output on the
283     /// - 0 = parity is disabled and no parity bit added to the data frame
284     /// - 1 = parity checking and generation is enabled.
286     /// See Table 3-11 on page 3-14 for the parity truth table.
290     /// - 0 = odd parity. The UART generates or checks for an odd number of 1s
291     ///   in the data and parity bits.
292     /// - 1 = even parity. The UART generates or checks for an even number of 1s
293     ///   in the data and parity bits.
295     /// and generation. See Table 3-11 on page 3-14 for the parity
298     /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits
300     /// logic does not check for two stop bits being received.
304     /// 1-byte-deep holding registers 1 = transmit and receive FIFO
307     /// WLEN Word length. These bits indicate the number of data bits
308     /// transmitted or received in a frame as follows: b11 = 8 bits
309     /// b10 = 7 bits
310     /// b01 = 6 bits
311     /// b00 = 5 bits.
319     /// the PEN bit disables parity checking and generation. See Table 3-11
320     /// on page 3-14 for the parity truth table.
322     /// 31:8 - Reserved, do not modify, read as zero.
329         // All the bits are cleared to 0 when reset.  in reset()
335     fn default() -> Self {  in default()
345     /// - 0 = odd parity. The UART generates or checks for an odd number of 1s
346     ///   in the data and parity bits.
348     /// - 1 = even parity. The UART generates or checks for an even number of 1s
349     ///   in the data and parity bits.
359     /// 1-byte-deep holding registers
369 /// These bits indicate the number of data bits transmitted or received in a
372     /// b11 = 8 bits
374     /// b10 = 7 bits
376     /// b01 = 6 bits
378     /// b00 = 5 bits.
384 /// The `UARTCR` register is the control register. All the bits are cleared
385 /// to `0` on reset except for bits `9` and `8` that are set to `1`.
388 /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
395     /// character before stopping. 1 = the UART is enabled. Data
401     /// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
407     /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
408     /// mode. If this bit is cleared to 0, low-level bits are transmitted as
410     /// this bit is set to 1, low-level bits are transmitted with a pulse
419     /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
421     /// be set to 1 to override the normal half-duplex SIR operation. This
432     /// of the UART is enabled. Data transmission occurs for either UART
438     /// of the UART is enabled. Data reception occurs for either UART
443     /// `DTR` Data transmit ready. This bit is the complement of the UART
444     /// data transmit ready, `nUARTDTR`, modem status output. That is, when
453     /// output is 0. For DTE this can be used as Data Carrier Detect (DCD).
460     /// RTS hardware flow control is enabled. Data is only requested when
464     /// CTS hardware flow control is enabled. Data is only transmitted when
467     /// 31:16 - Reserved, do not modify, read as zero.
481     fn default() -> Self {  in default()
488 /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC