Lines Matching defs:SDHCIState
34 struct SDHCIState { struct
36 union {
42 SDBus sdbus;
43 MemoryRegion iomem;
44 AddressSpace sysbus_dma_as;
45 AddressSpace *dma_as;
46 MemoryRegion *dma_mr;
47 const MemoryRegionOps *io_ops;
49 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
50 QEMUTimer *transfer_timer;
51 qemu_irq irq;
54 uint32_t sdmasysad; /* SDMA System Address register */
55 uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
56 uint16_t blkcnt; /* Blocks count for current transfer */
57 uint32_t argument; /* Command Argument Register */
58 uint16_t trnmod; /* Transfer Mode Setting Register */
59 uint16_t cmdreg; /* Command Register */
60 uint32_t rspreg[4]; /* Response Registers 0-3 */
61 uint32_t prnsts; /* Present State Register */
62 uint8_t hostctl1; /* Host Control Register */
63 uint8_t pwrcon; /* Power control Register */
64 uint8_t blkgap; /* Block Gap Control Register */
65 uint8_t wakcon; /* WakeUp Control Register */
66 uint16_t clkcon; /* Clock control Register */
67 uint8_t timeoutcon; /* Timeout Control Register */
68 uint8_t admaerr; /* ADMA Error Status Register */
69 uint16_t norintsts; /* Normal Interrupt Status Register */
70 uint16_t errintsts; /* Error Interrupt Status Register */
71 uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
72 uint16_t errintstsen; /* Error Interrupt Status Enable Register */
73 uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
74 uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
75 uint16_t acmd12errsts; /* Auto CMD12 error status register */
76 uint16_t hostctl2; /* Host Control 2 */
77 uint64_t admasysaddr; /* ADMA System Address Register */
78 uint16_t vendor_spec; /* Vendor specific register */
81 uint64_t capareg; /* Capabilities Register */
82 uint64_t maxcurr; /* Maximum Current Capabilities Register */
83 uint16_t version; /* Host Controller Version Register */
85 uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
109 typedef struct SDHCIState SDHCIState; argument