112 #define xive2_end_is_valid(end)    (be32_to_cpu((end)->w0) & END2_W0_VALID)  argument
113 #define xive2_end_is_enqueue(end)  (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)  argument
114 #define xive2_end_is_notify(end)                \  argument
115     (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
116 #define xive2_end_is_backlog(end)  (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)  argument
117 #define xive2_end_is_precluded_escalation(end)          \  argument
118     (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
119 #define xive2_end_is_escalate(end)                      \  argument
120     (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
121 #define xive2_end_is_uncond_escalation(end)              \  argument
122     (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
123 #define xive2_end_is_silent_escalation(end)              \  argument
124     (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
125 #define xive2_end_is_escalate_end(end)              \  argument
126     (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
127 #define xive2_end_is_firmware1(end)              \  argument
128     (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
129 #define xive2_end_is_firmware2(end)              \  argument
130     (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
131 #define xive2_end_is_ignore(end)                \  argument
132     (be32_to_cpu((end)->w6) & END2_W6_IGNORE)
133 #define xive2_end_is_crowd(end)                 \  argument
134     (be32_to_cpu((end)->w6) & END2_W6_CROWD)
136 static inline uint64_t xive2_end_qaddr(Xive2End *end)  in xive2_end_qaddr()  argument
138     return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |  in xive2_end_qaddr()
139         (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);  in xive2_end_qaddr()
142 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf);
143 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
145 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,