Lines Matching refs:be32_to_cpu

112 #define xive2_end_is_valid(end)    (be32_to_cpu((end)->w0) & END2_W0_VALID)
113 #define xive2_end_is_enqueue(end)  (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
115     (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
116 #define xive2_end_is_backlog(end)  (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
118     (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
120     (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
122     (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
124     (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
126     (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
128     (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
130     (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
132     (be32_to_cpu((end)->w6) & END2_W6_IGNORE)
134     (be32_to_cpu((end)->w6) & END2_W6_CROWD)
138     return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |  in xive2_end_qaddr()
139         (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);  in xive2_end_qaddr()
182 #define xive2_nvp_is_valid(nvp)    (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
183 #define xive2_nvp_is_hw(nvp)       (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
184 #define xive2_nvp_is_co(nvp)       (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
227 #define xive2_nvgc_is_valid(nvgc)    (be32_to_cpu((nvgc)->w0) & NVGC2_W0_VALID)