Lines Matching +full:0 +full:x1032
7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x0BFF */
15 #define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */
16 #define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */
17 #define GSB_VCPU_VPA 0x0C02 /* HRA to Guest VCPU VPA */
18 /* RESERVED 0x0C03 - 0x0FFF */
19 #define GSB_VCPU_GPR0 0x1000
20 #define GSB_VCPU_GPR1 0x1001
21 #define GSB_VCPU_GPR2 0x1002
22 #define GSB_VCPU_GPR3 0x1003
23 #define GSB_VCPU_GPR4 0x1004
24 #define GSB_VCPU_GPR5 0x1005
25 #define GSB_VCPU_GPR6 0x1006
26 #define GSB_VCPU_GPR7 0x1007
27 #define GSB_VCPU_GPR8 0x1008
28 #define GSB_VCPU_GPR9 0x1009
29 #define GSB_VCPU_GPR10 0x100A
30 #define GSB_VCPU_GPR11 0x100B
31 #define GSB_VCPU_GPR12 0x100C
32 #define GSB_VCPU_GPR13 0x100D
33 #define GSB_VCPU_GPR14 0x100E
34 #define GSB_VCPU_GPR15 0x100F
35 #define GSB_VCPU_GPR16 0x1010
36 #define GSB_VCPU_GPR17 0x1011
37 #define GSB_VCPU_GPR18 0x1012
38 #define GSB_VCPU_GPR19 0x1013
39 #define GSB_VCPU_GPR20 0x1014
40 #define GSB_VCPU_GPR21 0x1015
41 #define GSB_VCPU_GPR22 0x1016
42 #define GSB_VCPU_GPR23 0x1017
43 #define GSB_VCPU_GPR24 0x1018
44 #define GSB_VCPU_GPR25 0x1019
45 #define GSB_VCPU_GPR26 0x101A
46 #define GSB_VCPU_GPR27 0x101B
47 #define GSB_VCPU_GPR28 0x101C
48 #define GSB_VCPU_GPR29 0x101D
49 #define GSB_VCPU_GPR30 0x101E
50 #define GSB_VCPU_GPR31 0x101F
51 #define GSB_VCPU_HDEC_EXPIRY_TB 0x1020
52 #define GSB_VCPU_SPR_NIA 0x1021
53 #define GSB_VCPU_SPR_MSR 0x1022
54 #define GSB_VCPU_SPR_LR 0x1023
55 #define GSB_VCPU_SPR_XER 0x1024
56 #define GSB_VCPU_SPR_CTR 0x1025
57 #define GSB_VCPU_SPR_CFAR 0x1026
58 #define GSB_VCPU_SPR_SRR0 0x1027
59 #define GSB_VCPU_SPR_SRR1 0x1028
60 #define GSB_VCPU_SPR_DAR 0x1029
61 #define GSB_VCPU_DEC_EXPIRE_TB 0x102A
62 #define GSB_VCPU_SPR_VTB 0x102B
63 #define GSB_VCPU_SPR_LPCR 0x102C
64 #define GSB_VCPU_SPR_HFSCR 0x102D
65 #define GSB_VCPU_SPR_FSCR 0x102E
66 #define GSB_VCPU_SPR_FPSCR 0x102F
67 #define GSB_VCPU_SPR_DAWR0 0x1030
68 #define GSB_VCPU_SPR_DAWR1 0x1031
69 #define GSB_VCPU_SPR_CIABR 0x1032
70 #define GSB_VCPU_SPR_PURR 0x1033
71 #define GSB_VCPU_SPR_SPURR 0x1034
72 #define GSB_VCPU_SPR_IC 0x1035
73 #define GSB_VCPU_SPR_SPRG0 0x1036
74 #define GSB_VCPU_SPR_SPRG1 0x1037
75 #define GSB_VCPU_SPR_SPRG2 0x1038
76 #define GSB_VCPU_SPR_SPRG3 0x1039
77 #define GSB_VCPU_SPR_PPR 0x103A
78 #define GSB_VCPU_SPR_MMCR0 0x103B
79 #define GSB_VCPU_SPR_MMCR1 0x103C
80 #define GSB_VCPU_SPR_MMCR2 0x103D
81 #define GSB_VCPU_SPR_MMCR3 0x103E
82 #define GSB_VCPU_SPR_MMCRA 0x103F
83 #define GSB_VCPU_SPR_SIER 0x1040
84 #define GSB_VCPU_SPR_SIER2 0x1041
85 #define GSB_VCPU_SPR_SIER3 0x1042
86 #define GSB_VCPU_SPR_BESCR 0x1043
87 #define GSB_VCPU_SPR_EBBHR 0x1044
88 #define GSB_VCPU_SPR_EBBRR 0x1045
89 #define GSB_VCPU_SPR_AMR 0x1046
90 #define GSB_VCPU_SPR_IAMR 0x1047
91 #define GSB_VCPU_SPR_AMOR 0x1048
92 #define GSB_VCPU_SPR_UAMOR 0x1049
93 #define GSB_VCPU_SPR_SDAR 0x104A
94 #define GSB_VCPU_SPR_SIAR 0x104B
95 #define GSB_VCPU_SPR_DSCR 0x104C
96 #define GSB_VCPU_SPR_TAR 0x104D
97 #define GSB_VCPU_SPR_DEXCR 0x104E
98 #define GSB_VCPU_SPR_HDEXCR 0x104F
99 #define GSB_VCPU_SPR_HASHKEYR 0x1050
100 #define GSB_VCPU_SPR_HASHPKEYR 0x1051
101 #define GSB_VCPU_SPR_CTRL 0x1052
102 #define GSB_VCPU_SPR_DPDES 0x1053
103 /* RESERVED 0x1054 - 0x1FFF */
104 #define GSB_VCPU_SPR_CR 0x2000
105 #define GSB_VCPU_SPR_PIDR 0x2001
106 #define GSB_VCPU_SPR_DSISR 0x2002
107 #define GSB_VCPU_SPR_VSCR 0x2003
108 #define GSB_VCPU_SPR_VRSAVE 0x2004
109 #define GSB_VCPU_SPR_DAWRX0 0x2005
110 #define GSB_VCPU_SPR_DAWRX1 0x2006
111 #define GSB_VCPU_SPR_PMC1 0x2007
112 #define GSB_VCPU_SPR_PMC2 0x2008
113 #define GSB_VCPU_SPR_PMC3 0x2009
114 #define GSB_VCPU_SPR_PMC4 0x200A
115 #define GSB_VCPU_SPR_PMC5 0x200B
116 #define GSB_VCPU_SPR_PMC6 0x200C
117 #define GSB_VCPU_SPR_WORT 0x200D
118 #define GSB_VCPU_SPR_PSPB 0x200E
119 /* RESERVED 0x200F - 0x2FFF */
120 #define GSB_VCPU_SPR_VSR0 0x3000
121 #define GSB_VCPU_SPR_VSR1 0x3001
122 #define GSB_VCPU_SPR_VSR2 0x3002
123 #define GSB_VCPU_SPR_VSR3 0x3003
124 #define GSB_VCPU_SPR_VSR4 0x3004
125 #define GSB_VCPU_SPR_VSR5 0x3005
126 #define GSB_VCPU_SPR_VSR6 0x3006
127 #define GSB_VCPU_SPR_VSR7 0x3007
128 #define GSB_VCPU_SPR_VSR8 0x3008
129 #define GSB_VCPU_SPR_VSR9 0x3009
130 #define GSB_VCPU_SPR_VSR10 0x300A
131 #define GSB_VCPU_SPR_VSR11 0x300B
132 #define GSB_VCPU_SPR_VSR12 0x300C
133 #define GSB_VCPU_SPR_VSR13 0x300D
134 #define GSB_VCPU_SPR_VSR14 0x300E
135 #define GSB_VCPU_SPR_VSR15 0x300F
136 #define GSB_VCPU_SPR_VSR16 0x3010
137 #define GSB_VCPU_SPR_VSR17 0x3011
138 #define GSB_VCPU_SPR_VSR18 0x3012
139 #define GSB_VCPU_SPR_VSR19 0x3013
140 #define GSB_VCPU_SPR_VSR20 0x3014
141 #define GSB_VCPU_SPR_VSR21 0x3015
142 #define GSB_VCPU_SPR_VSR22 0x3016
143 #define GSB_VCPU_SPR_VSR23 0x3017
144 #define GSB_VCPU_SPR_VSR24 0x3018
145 #define GSB_VCPU_SPR_VSR25 0x3019
146 #define GSB_VCPU_SPR_VSR26 0x301A
147 #define GSB_VCPU_SPR_VSR27 0x301B
148 #define GSB_VCPU_SPR_VSR28 0x301C
149 #define GSB_VCPU_SPR_VSR29 0x301D
150 #define GSB_VCPU_SPR_VSR30 0x301E
151 #define GSB_VCPU_SPR_VSR31 0x301F
152 #define GSB_VCPU_SPR_VSR32 0x3020
153 #define GSB_VCPU_SPR_VSR33 0x3021
154 #define GSB_VCPU_SPR_VSR34 0x3022
155 #define GSB_VCPU_SPR_VSR35 0x3023
156 #define GSB_VCPU_SPR_VSR36 0x3024
157 #define GSB_VCPU_SPR_VSR37 0x3025
158 #define GSB_VCPU_SPR_VSR38 0x3026
159 #define GSB_VCPU_SPR_VSR39 0x3027
160 #define GSB_VCPU_SPR_VSR40 0x3028
161 #define GSB_VCPU_SPR_VSR41 0x3029
162 #define GSB_VCPU_SPR_VSR42 0x302A
163 #define GSB_VCPU_SPR_VSR43 0x302B
164 #define GSB_VCPU_SPR_VSR44 0x302C
165 #define GSB_VCPU_SPR_VSR45 0x302D
166 #define GSB_VCPU_SPR_VSR46 0x302E
167 #define GSB_VCPU_SPR_VSR47 0x302F
168 #define GSB_VCPU_SPR_VSR48 0x3030
169 #define GSB_VCPU_SPR_VSR49 0x3031
170 #define GSB_VCPU_SPR_VSR50 0x3032
171 #define GSB_VCPU_SPR_VSR51 0x3033
172 #define GSB_VCPU_SPR_VSR52 0x3034
173 #define GSB_VCPU_SPR_VSR53 0x3035
174 #define GSB_VCPU_SPR_VSR54 0x3036
175 #define GSB_VCPU_SPR_VSR55 0x3037
176 #define GSB_VCPU_SPR_VSR56 0x3038
177 #define GSB_VCPU_SPR_VSR57 0x3039
178 #define GSB_VCPU_SPR_VSR58 0x303A
179 #define GSB_VCPU_SPR_VSR59 0x303B
180 #define GSB_VCPU_SPR_VSR60 0x303C
181 #define GSB_VCPU_SPR_VSR61 0x303D
182 #define GSB_VCPU_SPR_VSR62 0x303E
183 #define GSB_VCPU_SPR_VSR63 0x303F
184 /* RESERVED 0x3040 - 0xEFFF */
185 #define GSB_VCPU_SPR_HDAR 0xF000
186 #define GSB_VCPU_SPR_HDSISR 0xF001
187 #define GSB_VCPU_SPR_HEIR 0xF002
188 #define GSB_VCPU_SPR_ASDR 0xF003
211 #define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
212 #define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
213 #define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
214 #define H_GUEST_CAPABILITIES_P11_MODE 0x1000000000000000
218 #define H_GUEST_CAP_COPY_MEM_BMAP 0
223 #define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
225 #define VCPU_OUT_BUF_MIN_SZ 0x80ULL
226 #define HVMASK_DEFAULT 0xffffffffffffffff
227 #define HVMASK_LPCR 0x0070000003820800
228 #define HVMASK_MSR 0xEBFFFFFFFFBFEFFF
229 #define HVMASK_HDEXCR 0x00000000FFFFFFFF
230 #define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF
232 #define H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE 0x8000000000000000
233 #define GUEST_STATE_REQUEST_GUEST_WIDE 0x1
234 #define GUEST_STATE_REQUEST_SET 0x2
238 * 0:2
285 .offset = 0, \
299 .offset = 0, \
511 #define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1
512 #define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x2