Lines Matching +full:sel +full:- +full:clk
29 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
31 /* Maximum amount of clock inputs in a SEL module. */
34 /* PLLs in CLK module. */
43 /* SEL/MUX in CLK module. */
57 /* Dividers in CLK module. */
86 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
88 * @clk: The CLK module that owns this module.
97 NPCM7xxCLKState *clk; member
105 * struct NPCM7xxClockSELState - A SEL module in CLK module.
107 * @clk: The CLK module that owns this module.
118 NPCM7xxCLKState *clk; member
128 * struct NPCM7xxClockDividerState - A Divider module in CLK module.
130 * @clk: The CLK module that owns this module.
143 NPCM7xxCLKState *clk; member
177 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"