Lines Matching +full:0 +full:x206000
67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
77 #define ARM_OFFSET 0xB000 /* ARM control block */
78 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
79 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
80 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
81 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
83 #define PM_OFFSET 0x100000 /* Power Management */
84 #define CPRMAN_OFFSET 0x101000 /* Clock Management */
85 #define AVS_OFFSET 0x103000 /* Audio Video Standard */
86 #define RNG_OFFSET 0x104000
87 #define GPIO_OFFSET 0x200000
88 #define UART0_OFFSET 0x201000 /* PL011 */
89 #define MMCI0_OFFSET 0x202000 /* Legacy MMC */
90 #define I2S_OFFSET 0x203000 /* PCM */
91 #define SPI0_OFFSET 0x204000 /* SPI master */
92 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
93 #define PIXV0_OFFSET 0x206000
94 #define PIXV1_OFFSET 0x207000
95 #define DPI_OFFSET 0x208000
96 #define DSI0_OFFSET 0x209000 /* Display Serial Interface */
97 #define PWM_OFFSET 0x20c000
98 #define PERM_OFFSET 0x20d000
99 #define TEC_OFFSET 0x20e000
100 #define OTP_OFFSET 0x20f000
101 #define SLIM_OFFSET 0x210000 /* SLIMbus */
102 #define CPG_OFFSET 0x211000
103 #define THERMAL_OFFSET 0x212000
104 #define AVSP_OFFSET 0x213000
105 #define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
106 #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
107 #define EMMC1_OFFSET 0x300000
108 #define EMMC2_OFFSET 0x340000
109 #define HVS_OFFSET 0x400000
110 #define SMI_OFFSET 0x600000
111 #define DSI1_OFFSET 0x700000
112 #define UCAM_OFFSET 0x800000
113 #define CMI_OFFSET 0x802000
114 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
115 #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
116 #define VECA_OFFSET 0x806000
117 #define PIXV2_OFFSET 0x807000
118 #define HDMI_OFFSET 0x808000
119 #define HDCP_OFFSET 0x809000
120 #define ARBR0_OFFSET 0x80a000
121 #define DBUS_OFFSET 0x900000
122 #define AVE0_OFFSET 0x910000
123 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
124 #define V3D_OFFSET 0xc00000
125 #define SDRAMC_OFFSET 0xe00000
126 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
127 #define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
128 #define ARBR1_OFFSET 0xe04000
129 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
130 #define DCRC_OFFSET 0xe07000
131 #define AXIP_OFFSET 0xe08000
134 #define INTERRUPT_TIMER0 0
200 #define INTERRUPT_ARM_TIMER 0