Lines Matching +full:x86 +full:- +full:openbsd
4 /* 32-bit ELF base types. */
11 /* 64-bit ELF base types. */
47 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
48 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
49 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
50 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
51 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
81 #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
89 #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */
95 #define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */
98 #define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
99 #define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */
100 #define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */
101 #define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */
102 #define MIPS_ABI_FP_XX 0x5 /* -mfpxx */
103 #define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
104 #define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
108 uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
110 /* - 0 for MIPS V and below, */
111 /* - 1-n otherwise. */
113 uint8_t cpr1_size; /* The size of co-processor 1 registers */
114 uint8_t cpr2_size; /* The size of co-processor 2 registers */
115 uint8_t fp_abi; /* The floating-point ABI */
116 uint32_t isa_ext; /* Mask of processor-specific extensions */
141 #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
143 #define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
156 #define EM_SPARCV9 43 /* SPARC v9 64-bit */
160 #define EM_IA_64 50 /* HP/Intel IA-64 */
162 #define EM_X86_64 62 /* AMD x86-64 */
166 #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
168 #define EM_AVR 83 /* AVR 8-bit microcontroller */
182 #define EM_RISCV 243 /* RISC-V */
202 #define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
333 #define AT_SECURE 23 /* boolean, was exec suid-like? */
341 #define AT_L1D_CACHESHAPE 35 /* bits 0-3: cache associativity. */
342 #define AT_L2_CACHESHAPE 36 /* bits 4-7: log2 of line size. */
367 #define ELF64_R_TYPE_DATA(i) (((ELF64_R_TYPE(i) >> 8) ^ 0x00800000) - 0x00800000)
510 #define HWCAP_ARM_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */
799 #define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */
806 /* Other constants defined in the ARM ELF spec. version B-01. */
827 /* ARM-specific values for sh_flags */
832 /* ARM-specific program header flags */
900 /* relocs to generate 19, 21, and 33 bit PC-relative addresses */
911 /* relocs for control-flow - all offsets as multiple of 4 */
916 /* group relocs to create pc-relative offset inline */
924 /* group relocs to create a GOT-relative offset inline */
932 /* GOT-relative data relocs */
935 /* GOT-relative instr relocs */
1084 /* x86-64 relocation types */
1124 #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
1125 #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
1126 #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
1156 #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
1161 #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */
1168 #define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */
1169 #define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */
1170 #define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */
1171 #define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */
1177 #define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */
1178 #define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */
1179 #define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */
1182 #define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */
1183 #define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */
1184 #define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */
1186 #define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */
1187 #define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */
1188 #define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */
1195 #define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */
1196 #define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */
1197 #define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */
1198 #define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */
1199 #define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */
1200 #define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */
1201 #define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */
1202 #define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */
1203 #define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */
1204 #define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */
1205 #define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */
1206 #define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */
1209 #define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */
1210 #define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */
1211 #define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */
1212 #define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */
1213 #define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */
1214 #define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */
1215 #define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */
1216 #define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */
1217 #define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */
1218 #define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */
1219 #define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */
1224 #define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */
1225 #define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */
1226 #define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */
1227 #define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */
1228 #define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/
1229 #define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */
1230 #define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */
1231 #define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */
1232 #define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */
1233 #define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */
1234 #define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */
1235 #define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */
1236 #define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */
1237 #define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/
1238 #define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/
1239 #define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */
1240 #define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */
1241 #define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */
1277 /* IA-64 specific declarations. */
1280 #define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
1281 #define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */
1303 /* IA-64 relocations. */
1366 #define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
1386 /* RISC-V relocations. */
1441 /* RISC-V ELF Flags. */
1639 #define ELFOSABI_HPUX 1 /* HP-UX */
1648 #define ELFOSABI_OPENBSD 12 /* OpenBSD. */
1685 #define NT_S390_VXRS_HIGH 0x30a /* s390 vector registers 16-31 */
1686 #define NT_S390_VXRS_LOW 0x309 /* s390 vector registers 0-15 (lower half) */
1724 * guest kernel, use this entry point to launch the guest in 32-bit