Lines Matching +full:xps +full:- +full:timer +full:- +full:1
2 * QEMU model of the Xilinx timer block.
6 * DS573: https://docs.amd.com/v/u/en-US/xps_timer
7 * LogiCORE IP XPS Timer/Counter (v1.02a)
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
42 #define R_TLR 1
46 #define TCSR_MDT (1<<0)
47 #define TCSR_UDT (1<<1)
48 #define TCSR_GENT (1<<2)
49 #define TCSR_CAPT (1<<3)
50 #define TCSR_ARHT (1<<4)
51 #define TCSR_LOAD (1<<5)
52 #define TCSR_ENIT (1<<6)
53 #define TCSR_ENT (1<<7)
54 #define TCSR_TINT (1<<8)
55 #define TCSR_PWMA (1<<9)
56 #define TCSR_ENALL (1<<10)
69 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
87 return 2 - t->one_timer_only; in num_timers()
102 csr = t->timers[i].regs[R_TCSR]; in timer_update_irq()
107 qemu_set_irq(t->irq, !!irq); in timer_update_irq()
116 unsigned int timer; in timer_read() local
119 timer = timer_from_addr(addr); in timer_read()
120 xt = &t->timers[timer]; in timer_read()
126 r = ptimer_get_count(xt->ptimer); in timer_read()
127 if (!(xt->regs[R_TCSR] & TCSR_UDT)) in timer_read()
130 timer, r, xt->regs[R_TCSR] & TCSR_UDT)); in timer_read()
133 if (addr < ARRAY_SIZE(xt->regs)) in timer_read()
134 r = xt->regs[addr]; in timer_read()
138 D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r)); in timer_read()
147 D(fprintf(stderr, "%s timer=%d down=%d\n", __func__, in timer_enable()
148 xt->nr, xt->regs[R_TCSR] & TCSR_UDT)); in timer_enable()
150 ptimer_stop(xt->ptimer); in timer_enable()
152 if (xt->regs[R_TCSR] & TCSR_UDT) in timer_enable()
153 count = xt->regs[R_TLR]; in timer_enable()
155 count = ~0 - xt->regs[R_TLR]; in timer_enable()
156 ptimer_set_limit(xt->ptimer, count, 1); in timer_enable()
157 ptimer_run(xt->ptimer, 1); in timer_enable()
166 unsigned int timer; in timer_write() local
170 timer = timer_from_addr(addr); in timer_write()
171 xt = &t->timers[timer]; in timer_write()
172 D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n", in timer_write()
173 __func__, addr * 4, value, timer, addr & 3)); in timer_write()
182 xt->regs[addr] = value & 0x7ff; in timer_write()
184 ptimer_transaction_begin(xt->ptimer); in timer_write()
186 ptimer_transaction_commit(xt->ptimer); in timer_write()
191 if (addr < ARRAY_SIZE(xt->regs)) in timer_write()
192 xt->regs[addr] = value; in timer_write()
199 [0 ... 1] = {
212 [1].endianness = DEVICE_BIG_ENDIAN,
218 XpsTimerState *t = xt->parent; in timer_hit()
219 D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); in timer_hit()
220 xt->regs[R_TCSR] |= TCSR_TINT; in timer_hit()
222 if (xt->regs[R_TCSR] & TCSR_ARHT) in timer_hit()
232 if (t->model_endianness == ENDIAN_MODE_UNSPECIFIED) { in xilinx_timer_realize()
239 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t)); in xilinx_timer_realize()
241 struct xlx_timer *xt = &t->timers[i]; in xilinx_timer_realize()
243 xt->parent = t; in xilinx_timer_realize()
244 xt->nr = i; in xilinx_timer_realize()
245 xt->ptimer = ptimer_init(timer_hit, xt, PTIMER_POLICY_LEGACY); in xilinx_timer_realize()
246 ptimer_transaction_begin(xt->ptimer); in xilinx_timer_realize()
247 ptimer_set_freq(xt->ptimer, t->freq_hz); in xilinx_timer_realize()
248 ptimer_transaction_commit(xt->ptimer); in xilinx_timer_realize()
251 memory_region_init_io(&t->mmio, OBJECT(t), in xilinx_timer_realize()
252 &timer_ops[t->model_endianness == ENDIAN_MODE_BIG], in xilinx_timer_realize()
253 t, "xlnx.xps-timer", R_MAX * 4 * num_timers(t)); in xilinx_timer_realize()
254 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio); in xilinx_timer_realize()
262 sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq); in xilinx_timer_init()
267 DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
268 DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
275 dc->realize = xilinx_timer_realize; in xilinx_timer_class_init()