Lines Matching refs:tm
81 PXA2xxTimer0 tm; member
148 timer_del(s->tm4[n].tm.qtimer); in pxa2xx_timer_update4()
156 new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), in pxa2xx_timer_update4()
158 timer_mod(s->tm4[n].tm.qtimer, new_qemu); in pxa2xx_timer_update4()
165 int tm = 0; in pxa2xx_timer_read() local
168 case OSMR3: tm ++; in pxa2xx_timer_read()
170 case OSMR2: tm ++; in pxa2xx_timer_read()
172 case OSMR1: tm ++; in pxa2xx_timer_read()
175 return s->timer[tm].value; in pxa2xx_timer_read()
176 case OSMR11: tm ++; in pxa2xx_timer_read()
178 case OSMR10: tm ++; in pxa2xx_timer_read()
180 case OSMR9: tm ++; in pxa2xx_timer_read()
182 case OSMR8: tm ++; in pxa2xx_timer_read()
184 case OSMR7: tm ++; in pxa2xx_timer_read()
186 case OSMR6: tm ++; in pxa2xx_timer_read()
188 case OSMR5: tm ++; in pxa2xx_timer_read()
193 return s->tm4[tm].tm.value; in pxa2xx_timer_read()
197 case OSCR11: tm ++; in pxa2xx_timer_read()
199 case OSCR10: tm ++; in pxa2xx_timer_read()
201 case OSCR9: tm ++; in pxa2xx_timer_read()
203 case OSCR8: tm ++; in pxa2xx_timer_read()
205 case OSCR7: tm ++; in pxa2xx_timer_read()
207 case OSCR6: tm ++; in pxa2xx_timer_read()
209 case OSCR5: tm ++; in pxa2xx_timer_read()
215 if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { in pxa2xx_timer_read()
216 if (s->tm4[tm - 1].freq) in pxa2xx_timer_read()
217 s->snapshot = s->tm4[tm - 1].clock + muldiv64( in pxa2xx_timer_read()
219 s->tm4[tm - 1].lastload, in pxa2xx_timer_read()
220 s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND); in pxa2xx_timer_read()
222 s->snapshot = s->tm4[tm - 1].clock; in pxa2xx_timer_read()
225 if (!s->tm4[tm].freq) in pxa2xx_timer_read()
226 return s->tm4[tm].clock; in pxa2xx_timer_read()
227 return s->tm4[tm].clock + in pxa2xx_timer_read()
229 s->tm4[tm].lastload, s->tm4[tm].freq, in pxa2xx_timer_read()
237 case OMCR11: tm ++; in pxa2xx_timer_read()
239 case OMCR10: tm ++; in pxa2xx_timer_read()
241 case OMCR9: tm ++; in pxa2xx_timer_read()
243 case OMCR8: tm ++; in pxa2xx_timer_read()
245 case OMCR7: tm ++; in pxa2xx_timer_read()
247 case OMCR6: tm ++; in pxa2xx_timer_read()
249 case OMCR5: tm ++; in pxa2xx_timer_read()
254 return s->tm4[tm].control; in pxa2xx_timer_read()
274 int i, tm = 0; in pxa2xx_timer_write() local
278 case OSMR3: tm ++; in pxa2xx_timer_write()
280 case OSMR2: tm ++; in pxa2xx_timer_write()
282 case OSMR1: tm ++; in pxa2xx_timer_write()
285 s->timer[tm].value = value; in pxa2xx_timer_write()
288 case OSMR11: tm ++; in pxa2xx_timer_write()
290 case OSMR10: tm ++; in pxa2xx_timer_write()
292 case OSMR9: tm ++; in pxa2xx_timer_write()
294 case OSMR8: tm ++; in pxa2xx_timer_write()
296 case OSMR7: tm ++; in pxa2xx_timer_write()
298 case OSMR6: tm ++; in pxa2xx_timer_write()
300 case OSMR5: tm ++; in pxa2xx_timer_write()
305 s->tm4[tm].tm.value = value; in pxa2xx_timer_write()
306 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); in pxa2xx_timer_write()
314 case OSCR11: tm ++; in pxa2xx_timer_write()
316 case OSCR10: tm ++; in pxa2xx_timer_write()
318 case OSCR9: tm ++; in pxa2xx_timer_write()
320 case OSCR8: tm ++; in pxa2xx_timer_write()
322 case OSCR7: tm ++; in pxa2xx_timer_write()
324 case OSCR6: tm ++; in pxa2xx_timer_write()
326 case OSCR5: tm ++; in pxa2xx_timer_write()
331 s->tm4[tm].oldclock = s->tm4[tm].clock; in pxa2xx_timer_write()
332 s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in pxa2xx_timer_write()
333 s->tm4[tm].clock = value; in pxa2xx_timer_write()
334 pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); in pxa2xx_timer_write()
351 case OMCR7: tm ++; in pxa2xx_timer_write()
353 case OMCR6: tm ++; in pxa2xx_timer_write()
355 case OMCR5: tm ++; in pxa2xx_timer_write()
360 s->tm4[tm].control = value & 0x0ff; in pxa2xx_timer_write()
362 if ((value & (1 << 7)) || tm == 0) in pxa2xx_timer_write()
363 s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7]; in pxa2xx_timer_write()
365 s->tm4[tm].freq = 0; in pxa2xx_timer_write()
366 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); in pxa2xx_timer_write()
369 case OMCR11: tm ++; in pxa2xx_timer_write()
371 case OMCR10: tm ++; in pxa2xx_timer_write()
373 case OMCR9: tm ++; in pxa2xx_timer_write()
375 case OMCR8: tm += 4; in pxa2xx_timer_write()
378 s->tm4[tm].control = value & 0x3ff; in pxa2xx_timer_write()
380 if ((value & (1 << 7)) || !(tm & 1)) in pxa2xx_timer_write()
381 s->tm4[tm].freq = in pxa2xx_timer_write()
384 s->tm4[tm].freq = 0; in pxa2xx_timer_write()
385 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); in pxa2xx_timer_write()
426 PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; in pxa2xx_timer_tick4()
428 pxa2xx_timer_tick(&t->tm); in pxa2xx_timer_tick4()
432 pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4); in pxa2xx_timer_tick4()
488 s->tm4[i].tm.value = 0; in pxa2xx_timer_realize()
489 s->tm4[i].tm.info = s; in pxa2xx_timer_realize()
490 s->tm4[i].tm.num = i + 4; in pxa2xx_timer_realize()
493 s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in pxa2xx_timer_realize()
514 VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,