Lines Matching refs:FIELD

39     FIELD(CONFIG_REG, IDLE_FLD, 31, 1)
40     FIELD(CONFIG_REG, DUAL_BYTE_OPCODE_EN_FLD, 30, 1)
41     FIELD(CONFIG_REG, CRC_ENABLE_FLD, 29, 1)
42     FIELD(CONFIG_REG, CONFIG_RESV2_FLD, 26, 3)
43     FIELD(CONFIG_REG, PIPELINE_PHY_FLD, 25, 1)
44     FIELD(CONFIG_REG, ENABLE_DTR_PROTOCOL_FLD, 24, 1)
45     FIELD(CONFIG_REG, ENABLE_AHB_DECODER_FLD, 23, 1)
46     FIELD(CONFIG_REG, MSTR_BAUD_DIV_FLD, 19, 4)
47     FIELD(CONFIG_REG, ENTER_XIP_MODE_IMM_FLD, 18, 1)
48     FIELD(CONFIG_REG, ENTER_XIP_MODE_FLD, 17, 1)
49     FIELD(CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD, 16, 1)
50     FIELD(CONFIG_REG, ENB_DMA_IF_FLD, 15, 1)
51     FIELD(CONFIG_REG, WR_PROT_FLASH_FLD, 14, 1)
52     FIELD(CONFIG_REG, PERIPH_CS_LINES_FLD, 10, 4)
53     FIELD(CONFIG_REG, PERIPH_SEL_DEC_FLD, 9, 1)
54     FIELD(CONFIG_REG, ENB_LEGACY_IP_MODE_FLD, 8, 1)
55     FIELD(CONFIG_REG, ENB_DIR_ACC_CTLR_FLD, 7, 1)
56     FIELD(CONFIG_REG, RESET_CFG_FLD, 6, 1)
57     FIELD(CONFIG_REG, RESET_PIN_FLD, 5, 1)
58     FIELD(CONFIG_REG, HOLD_PIN_FLD, 4, 1)
59     FIELD(CONFIG_REG, PHY_MODE_ENABLE_FLD, 3, 1)
60     FIELD(CONFIG_REG, SEL_CLK_PHASE_FLD, 2, 1)
61     FIELD(CONFIG_REG, SEL_CLK_POL_FLD, 1, 1)
62     FIELD(CONFIG_REG, ENB_SPI_FLD, 0, 1)
64     FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV5_FLD, 29, 3)
65     FIELD(DEV_INSTR_RD_CONFIG_REG, DUMMY_RD_CLK_CYCLES_FLD, 24, 5)
66     FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV4_FLD, 21, 3)
67     FIELD(DEV_INSTR_RD_CONFIG_REG, MODE_BIT_ENABLE_FLD, 20, 1)
68     FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV3_FLD, 18, 2)
69     FIELD(DEV_INSTR_RD_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2)
70     FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV2_FLD, 14, 2)
71     FIELD(DEV_INSTR_RD_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2)
72     FIELD(DEV_INSTR_RD_CONFIG_REG, PRED_DIS_FLD, 11, 1)
73     FIELD(DEV_INSTR_RD_CONFIG_REG, DDR_EN_FLD, 10, 1)
74     FIELD(DEV_INSTR_RD_CONFIG_REG, INSTR_TYPE_FLD, 8, 2)
75     FIELD(DEV_INSTR_RD_CONFIG_REG, RD_OPCODE_NON_XIP_FLD, 0, 8)
77     FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV4_FLD, 29, 3)
78     FIELD(DEV_INSTR_WR_CONFIG_REG, DUMMY_WR_CLK_CYCLES_FLD, 24, 5)
79     FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV3_FLD, 18, 6)
80     FIELD(DEV_INSTR_WR_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2)
81     FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV2_FLD, 14, 2)
82     FIELD(DEV_INSTR_WR_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2)
83     FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV1_FLD, 9, 3)
84     FIELD(DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD, 8, 1)
85     FIELD(DEV_INSTR_WR_CONFIG_REG, WR_OPCODE_FLD, 0, 8)
87     FIELD(DEV_DELAY_REG, D_NSS_FLD, 24, 8)
88     FIELD(DEV_DELAY_REG, D_BTWN_FLD, 16, 8)
89     FIELD(DEV_DELAY_REG, D_AFTER_FLD, 8, 8)
90     FIELD(DEV_DELAY_REG, D_INIT_FLD, 0, 8)
92     FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV3_FLD, 20, 12)
93     FIELD(RD_DATA_CAPTURE_REG, DDR_READ_DELAY_FLD, 16, 4)
94     FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV2_FLD, 9, 7)
95     FIELD(RD_DATA_CAPTURE_REG, DQS_ENABLE_FLD, 8, 1)
96     FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV1_FLD, 6, 2)
97     FIELD(RD_DATA_CAPTURE_REG, SAMPLE_EDGE_SEL_FLD, 5, 1)
98     FIELD(RD_DATA_CAPTURE_REG, DELAY_FLD, 1, 4)
99     FIELD(RD_DATA_CAPTURE_REG, BYPASS_FLD, 0, 1)
101     FIELD(DEV_SIZE_CONFIG_REG, DEV_SIZE_RESV_FLD, 29, 3)
102     FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS3_FLD, 27, 2)
103     FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS2_FLD, 25, 2)
104     FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS1_FLD, 23, 2)
105     FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS0_FLD, 21, 2)
106     FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_SUBSECTOR_FLD, 16, 5)
107     FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_DEVICE_PAGE_FLD, 4, 12)
108     FIELD(DEV_SIZE_CONFIG_REG, NUM_ADDR_BYTES_FLD, 0, 4)
110     FIELD(SRAM_PARTITION_CFG_REG, SRAM_PARTITION_RESV_FLD, 8, 24)
111     FIELD(SRAM_PARTITION_CFG_REG, ADDR_FLD, 0, 8)
114     FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV2_FLD, 12, 20)
115     FIELD(DMA_PERIPH_CONFIG_REG, NUM_BURST_REQ_BYTES_FLD, 8, 4)
116     FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV1_FLD, 4, 4)
117     FIELD(DMA_PERIPH_CONFIG_REG, NUM_SINGLE_REQ_BYTES_FLD, 0, 4)
120     FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_LOW_FLD, 24, 8)
121     FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_UP_FLD, 16, 8)
122     FIELD(MODE_BIT_CONFIG_REG, CRC_OUT_ENABLE_FLD, 15, 1)
123     FIELD(MODE_BIT_CONFIG_REG, MODE_BIT_RESV1_FLD, 11, 4)
124     FIELD(MODE_BIT_CONFIG_REG, CHUNK_SIZE_FLD, 8, 3)
125     FIELD(MODE_BIT_CONFIG_REG, MODE_FLD, 0, 8)
127     FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_WRITE_FLD, 16, 16)
128     FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_READ_FLD, 0, 16)
130     FIELD(TX_THRESH_REG, TX_THRESH_RESV_FLD, 5, 27)
131     FIELD(TX_THRESH_REG, LEVEL_FLD, 0, 5)
133     FIELD(RX_THRESH_REG, RX_THRESH_RESV_FLD, 5, 27)
134     FIELD(RX_THRESH_REG, LEVEL_FLD, 0, 5)
136     FIELD(WRITE_COMPLETION_CTRL_REG, POLL_REP_DELAY_FLD, 24, 8)
137     FIELD(WRITE_COMPLETION_CTRL_REG, POLL_COUNT_FLD, 16, 8)
138     FIELD(WRITE_COMPLETION_CTRL_REG, ENABLE_POLLING_EXP_FLD, 15, 1)
139     FIELD(WRITE_COMPLETION_CTRL_REG, DISABLE_POLLING_FLD, 14, 1)
140     FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_POLARITY_FLD, 13, 1)
141     FIELD(WRITE_COMPLETION_CTRL_REG, WR_COMP_CTRL_RESV1_FLD, 12, 1)
142     FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_ADDR_EN_FLD, 11, 1)
143     FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_BIT_INDEX_FLD, 8, 3)
144     FIELD(WRITE_COMPLETION_CTRL_REG, OPCODE_FLD, 0, 8)
147     FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV_FLD, 20, 12)
148     FIELD(IRQ_STATUS_REG, ECC_FAIL_FLD, 19, 1)
149     FIELD(IRQ_STATUS_REG, TX_CRC_CHUNK_BRK_FLD, 18, 1)
150     FIELD(IRQ_STATUS_REG, RX_CRC_DATA_VAL_FLD, 17, 1)
151     FIELD(IRQ_STATUS_REG, RX_CRC_DATA_ERR_FLD, 16, 1)
152     FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV1_FLD, 15, 1)
153     FIELD(IRQ_STATUS_REG, STIG_REQ_INT_FLD, 14, 1)
154     FIELD(IRQ_STATUS_REG, POLL_EXP_INT_FLD, 13, 1)
155     FIELD(IRQ_STATUS_REG, INDRD_SRAM_FULL_FLD, 12, 1)
156     FIELD(IRQ_STATUS_REG, RX_FIFO_FULL_FLD, 11, 1)
157     FIELD(IRQ_STATUS_REG, RX_FIFO_NOT_EMPTY_FLD, 10, 1)
158     FIELD(IRQ_STATUS_REG, TX_FIFO_FULL_FLD, 9, 1)
159     FIELD(IRQ_STATUS_REG, TX_FIFO_NOT_FULL_FLD, 8, 1)
160     FIELD(IRQ_STATUS_REG, RECV_OVERFLOW_FLD, 7, 1)
161     FIELD(IRQ_STATUS_REG, INDIRECT_XFER_LEVEL_BREACH_FLD, 6, 1)
162     FIELD(IRQ_STATUS_REG, ILLEGAL_ACCESS_DET_FLD, 5, 1)
163     FIELD(IRQ_STATUS_REG, PROT_WR_ATTEMPT_FLD, 4, 1)
164     FIELD(IRQ_STATUS_REG, INDIRECT_TRANSFER_REJECT_FLD, 3, 1)
165     FIELD(IRQ_STATUS_REG, INDIRECT_OP_DONE_FLD, 2, 1)
166     FIELD(IRQ_STATUS_REG, UNDERFLOW_DET_FLD, 1, 1)
167     FIELD(IRQ_STATUS_REG, MODE_M_FAIL_FLD, 0, 1)
169     FIELD(IRQ_MASK_REG, IRQ_MASK_RESV_FLD, 20, 12)
170     FIELD(IRQ_MASK_REG, ECC_FAIL_MASK_FLD, 19, 1)
171     FIELD(IRQ_MASK_REG, TX_CRC_CHUNK_BRK_MASK_FLD, 18, 1)
172     FIELD(IRQ_MASK_REG, RX_CRC_DATA_VAL_MASK_FLD, 17, 1)
173     FIELD(IRQ_MASK_REG, RX_CRC_DATA_ERR_MASK_FLD, 16, 1)
174     FIELD(IRQ_MASK_REG, IRQ_MASK_RESV1_FLD, 15, 1)
175     FIELD(IRQ_MASK_REG, STIG_REQ_MASK_FLD, 14, 1)
176     FIELD(IRQ_MASK_REG, POLL_EXP_INT_MASK_FLD, 13, 1)
177     FIELD(IRQ_MASK_REG, INDRD_SRAM_FULL_MASK_FLD, 12, 1)
178     FIELD(IRQ_MASK_REG, RX_FIFO_FULL_MASK_FLD, 11, 1)
179     FIELD(IRQ_MASK_REG, RX_FIFO_NOT_EMPTY_MASK_FLD, 10, 1)
180     FIELD(IRQ_MASK_REG, TX_FIFO_FULL_MASK_FLD, 9, 1)
181     FIELD(IRQ_MASK_REG, TX_FIFO_NOT_FULL_MASK_FLD, 8, 1)
182     FIELD(IRQ_MASK_REG, RECV_OVERFLOW_MASK_FLD, 7, 1)
183     FIELD(IRQ_MASK_REG, INDIRECT_XFER_LEVEL_BREACH_MASK_FLD, 6, 1)
184     FIELD(IRQ_MASK_REG, ILLEGAL_ACCESS_DET_MASK_FLD, 5, 1)
185     FIELD(IRQ_MASK_REG, PROT_WR_ATTEMPT_MASK_FLD, 4, 1)
186     FIELD(IRQ_MASK_REG, INDIRECT_TRANSFER_REJECT_MASK_FLD, 3, 1)
187     FIELD(IRQ_MASK_REG, INDIRECT_OP_DONE_MASK_FLD, 2, 1)
188     FIELD(IRQ_MASK_REG, UNDERFLOW_DET_MASK_FLD, 1, 1)
189     FIELD(IRQ_MASK_REG, MODE_M_FAIL_MASK_FLD, 0, 1)
193     FIELD(WR_PROT_CTRL_REG, WR_PROT_CTRL_RESV_FLD, 2, 30)
194     FIELD(WR_PROT_CTRL_REG, ENB_FLD, 1, 1)
195     FIELD(WR_PROT_CTRL_REG, INV_FLD, 0, 1)
197     FIELD(INDIRECT_READ_XFER_CTRL_REG, INDIR_RD_XFER_RESV_FLD, 8, 24)
198     FIELD(INDIRECT_READ_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2)
199     FIELD(INDIRECT_READ_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1)
200     FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_QUEUED_FLD, 4, 1)
201     FIELD(INDIRECT_READ_XFER_CTRL_REG, SRAM_FULL_FLD, 3, 1)
202     FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_STATUS_FLD, 2, 1)
203     FIELD(INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD, 1, 1)
204     FIELD(INDIRECT_READ_XFER_CTRL_REG, START_FLD, 0, 1)
209     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV2_FLD, 8, 24)
210     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2)
211     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1)
212     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_QUEUED_FLD, 4, 1)
213     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV1_FLD, 3, 1)
214     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_STATUS_FLD, 2, 1)
215     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD, 1, 1)
216     FIELD(INDIRECT_WRITE_XFER_CTRL_REG, START_FLD, 0, 1)
221     FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_RESV1_FLD, 4, 28)
222     FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_WIDTH_FLD, 0, 4)
224     FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV1_FLD, 29, 3)
225     FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_ADDR_FLD, 20, 9)
226     FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV2_FLD, 19, 1)
227     FIELD(FLASH_COMMAND_CTRL_MEM_REG, NB_OF_STIG_READ_BYTES_FLD, 16, 3)
228     FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_READ_DATA_FLD, 8, 8)
229     FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV3_FLD, 2, 6)
230     FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_REQ_IN_PROGRESS_FLD, 1, 1)
231     FIELD(FLASH_COMMAND_CTRL_MEM_REG, TRIGGER_MEM_BANK_REQ_FLD, 0, 1)
233     FIELD(FLASH_CMD_CTRL_REG, CMD_OPCODE_FLD, 24, 8)
234     FIELD(FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD, 23, 1)
235     FIELD(FLASH_CMD_CTRL_REG, NUM_RD_DATA_BYTES_FLD, 20, 3)
236     FIELD(FLASH_CMD_CTRL_REG, ENB_COMD_ADDR_FLD, 19, 1)
237     FIELD(FLASH_CMD_CTRL_REG, ENB_MODE_BIT_FLD, 18, 1)
238     FIELD(FLASH_CMD_CTRL_REG, NUM_ADDR_BYTES_FLD, 16, 2)
239     FIELD(FLASH_CMD_CTRL_REG, ENB_WRITE_DATA_FLD, 15, 1)
240     FIELD(FLASH_CMD_CTRL_REG, NUM_WR_DATA_BYTES_FLD, 12, 3)
241     FIELD(FLASH_CMD_CTRL_REG, NUM_DUMMY_CYCLES_FLD, 7, 5)
242     FIELD(FLASH_CMD_CTRL_REG, FLASH_CMD_CTRL_RESV1_FLD, 3, 4)
243     FIELD(FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD, 2, 1)
244     FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_STATUS_FLD, 1, 1)
245     FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0, 1)
252     FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD2, 21, 11)
253     FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_NB_DUMMY, 16, 5)
254     FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD1, 9, 7)
255     FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_VALID_FLD, 8, 1)
256     FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_FLD, 0, 8)
258     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESYNC_FLD, 31, 1)
259     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESET_FLD, 30, 1)
260     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_BYPASS_FLD, 29, 1)
261     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV2_FLD, 23, 6)
262     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_TX_DLL_DELAY_FLD, 16, 7)
263     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV1_FLD, 7, 9)
264     FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_DELAY_FLD, 0, 7)
266     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV3_FLD, 25, 7)
267     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_LOCK_MODE_FLD, 24, 1)
268     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_BYPASS_MODE_FLD, 23, 1)
269     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_PHASE_DETECT_SELECTOR_FLD, 20, 3)
270     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV2_FLD, 19, 1)
271     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_NB_INDICATIONS_FLD, 16, 3)
272     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV1_FLD, 7, 9)
273     FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_INITIAL_DELAY_FLD, 0, 7)
275     FIELD(DLL_OBSERVABLE_LOWER_REG,
277     FIELD(DLL_OBSERVABLE_LOWER_REG,
279     FIELD(DLL_OBSERVABLE_LOWER_REG,
281     FIELD(DLL_OBSERVABLE_LOWER_REG,
283     FIELD(DLL_OBSERVABLE_LOWER_REG,
285     FIELD(DLL_OBSERVABLE_LOWER_REG,
287     FIELD(DLL_OBSERVABLE_LOWER_REG,
290     FIELD(DLL_OBSERVABLE_UPPER_REG,
292     FIELD(DLL_OBSERVABLE_UPPER_REG,
294     FIELD(DLL_OBSERVABLE_UPPER_REG,
296     FIELD(DLL_OBSERVABLE_UPPER_REG,
299     FIELD(OPCODE_EXT_LOWER_REG, EXT_READ_OPCODE_FLD, 24, 8)
300     FIELD(OPCODE_EXT_LOWER_REG, EXT_WRITE_OPCODE_FLD, 16, 8)
301     FIELD(OPCODE_EXT_LOWER_REG, EXT_POLL_OPCODE_FLD, 8, 8)
302     FIELD(OPCODE_EXT_LOWER_REG, EXT_STIG_OPCODE_FLD, 0, 8)
304     FIELD(OPCODE_EXT_UPPER_REG, WEL_OPCODE_FLD, 24, 8)
305     FIELD(OPCODE_EXT_UPPER_REG, EXT_WEL_OPCODE_FLD, 16, 8)
306     FIELD(OPCODE_EXT_UPPER_REG, OPCODE_EXT_UPPER_RESV1_FLD, 0, 16)
308     FIELD(MODULE_ID_REG, FIX_PATCH_FLD, 24, 8)
309     FIELD(MODULE_ID_REG, MODULE_ID_FLD, 8, 16)
310     FIELD(MODULE_ID_REG, MODULE_ID_RESV_FLD, 2, 6)
311     FIELD(MODULE_ID_REG, CONF_FLD, 0, 2)