2  * QEMU model of the Xilinx SPI Controller
35 #include "hw/qdev-properties.h"
36 #include "hw/qdev-properties-system.h"
53 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
54 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
55 #define IRQ_DRR_FULL         (1 << (31 - 27))
58 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
69 #define SR_TX_EMPTY   (1 << 2)
82 #define TYPE_XILINX_SPI "xlnx.xps-spi"
97     SSIBus *spi;  member
107     fifo8_reset(&s->tx_fifo);  in txfifo_reset()
109     s->regs[R_SPISR] &= ~SR_TX_FULL;  in txfifo_reset()
110     s->regs[R_SPISR] |= SR_TX_EMPTY;  in txfifo_reset()
115     fifo8_reset(&s->rx_fifo);  in rxfifo_reset()
117     s->regs[R_SPISR] |= SR_RX_EMPTY;  in rxfifo_reset()
118     s->regs[R_SPISR] &= ~SR_RX_FULL;  in rxfifo_reset()
125     for (i = 0; i < s->num_cs; ++i) {  in xlx_spi_update_cs()
126         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));  in xlx_spi_update_cs()
134     s->regs[R_IPISR] |=  in xlx_spi_update_irq()
135             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |  in xlx_spi_update_irq()
136             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);  in xlx_spi_update_irq()
138     pending = s->regs[R_IPISR] & s->regs[R_IPIER];  in xlx_spi_update_irq()
140     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);  in xlx_spi_update_irq()
145     if (pending != s->irqline) {  in xlx_spi_update_irq()
146         s->irqline = pending;  in xlx_spi_update_irq()
148                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);  in xlx_spi_update_irq()
149         qemu_set_irq(s->irq, pending);  in xlx_spi_update_irq()
156     memset(s->regs, 0, sizeof s->regs);  in xlx_spi_do_reset()
161     s->regs[R_SPISSR] = ~0;  in xlx_spi_do_reset()
162     s->regs[R_SPICR] = R_SPICR_MTI;  in xlx_spi_do_reset()
174     return !(s->regs[R_SPICR] & R_SPICR_MTI);  in spi_master_enabled()
182     while (!fifo8_is_empty(&s->tx_fifo)) {  in spi_flush_txfifo()
183         tx = (uint32_t)fifo8_pop(&s->tx_fifo);  in spi_flush_txfifo()
185         rx = ssi_transfer(s->spi, tx);  in spi_flush_txfifo()
187         if (fifo8_is_full(&s->rx_fifo)) {  in spi_flush_txfifo()
188             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;  in spi_flush_txfifo()
190             fifo8_push(&s->rx_fifo, (uint8_t)rx);  in spi_flush_txfifo()
191             if (fifo8_is_full(&s->rx_fifo)) {  in spi_flush_txfifo()
192                 s->regs[R_SPISR] |= SR_RX_FULL;  in spi_flush_txfifo()
193                 s->regs[R_IPISR] |= IRQ_DRR_FULL;  in spi_flush_txfifo()
197         s->regs[R_SPISR] &= ~SR_RX_EMPTY;  in spi_flush_txfifo()
198         s->regs[R_SPISR] &= ~SR_TX_FULL;  in spi_flush_txfifo()
199         s->regs[R_SPISR] |= SR_TX_EMPTY;  in spi_flush_txfifo()
201         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;  in spi_flush_txfifo()
202         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;  in spi_flush_txfifo()
213     addr >>= 2;  in spi_read()
216         if (fifo8_is_empty(&s->rx_fifo)) {  in spi_read()
221         s->regs[R_SPISR] &= ~SR_RX_FULL;  in spi_read()
222         r = fifo8_pop(&s->rx_fifo);  in spi_read()
223         if (fifo8_is_empty(&s->rx_fifo)) {  in spi_read()
224             s->regs[R_SPISR] |= SR_RX_EMPTY;  in spi_read()
229         r = s->regs[addr];  in spi_read()
233         if (addr < ARRAY_SIZE(s->regs)) {  in spi_read()
234             r = s->regs[addr];  in spi_read()
252     addr >>= 2;  in spi_write()
263         s->regs[R_SPISR] &= ~SR_TX_EMPTY;  in spi_write()
264         fifo8_push(&s->tx_fifo, (uint8_t)value);  in spi_write()
265         if (fifo8_is_full(&s->tx_fifo)) {  in spi_write()
266             s->regs[R_SPISR] |= SR_TX_FULL;  in spi_write()
282         s->regs[addr] ^= value;  in spi_write()
287         s->regs[addr] = value;  in spi_write()
301         s->regs[addr] = value;  in spi_write()
309         if (addr < ARRAY_SIZE(s->regs)) {  in spi_write()
310             s->regs[addr] = value;  in spi_write()
319 static const MemoryRegionOps spi_ops[2] = {
338     if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {  in xilinx_spi_realize()
346     s->spi = ssi_create_bus(dev, "spi");  in xilinx_spi_realize()
348     sysbus_init_irq(sbd, &s->irq);  in xilinx_spi_realize()
349     s->cs_lines = g_new0(qemu_irq, s->num_cs);  in xilinx_spi_realize()
350     for (i = 0; i < s->num_cs; ++i) {  in xilinx_spi_realize()
351         sysbus_init_irq(sbd, &s->cs_lines[i]);  in xilinx_spi_realize()
354     memory_region_init_io(&s->mmio, OBJECT(s),  in xilinx_spi_realize()
355                           &spi_ops[s->model_endianness == ENDIAN_MODE_BIG], s,  in xilinx_spi_realize()
356                           "xilinx-spi", R_MAX * 4);  in xilinx_spi_realize()
357     sysbus_init_mmio(sbd, &s->mmio);  in xilinx_spi_realize()
359     s->irqline = -1;  in xilinx_spi_realize()
361     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);  in xilinx_spi_realize()
362     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);  in xilinx_spi_realize()
379     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
386     dc->realize = xilinx_spi_realize;  in xilinx_spi_class_init()
389     dc->vmsd = &vmstate_xilinx_spi;  in xilinx_spi_class_init()