141 #define R_DMA_CTRL        (0x80 / 4)  macro
821         (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||  in aspeed_smc_read()
871         (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;  in aspeed_smc_dma_calibration()
873         (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;  in aspeed_smc_dma_calibration()
908         (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;  in aspeed_smc_inject_read_failure()
910         (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;  in aspeed_smc_inject_read_failure()
952     if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {  in aspeed_smc_dma_checksum()
957     if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {  in aspeed_smc_dma_checksum()
1007     trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?  in aspeed_smc_dma_rw()
1013         if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {  in aspeed_smc_dma_rw()
1085     return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&  in aspeed_smc_dma_in_progress()
1100         s->regs[R_DMA_CTRL] = dma_ctrl;  in aspeed_smc_dma_ctrl()
1111     s->regs[R_DMA_CTRL] = dma_ctrl;  in aspeed_smc_dma_ctrl()
1113     if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {  in aspeed_smc_dma_ctrl()
1130     if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {  in aspeed_smc_dma_granted()
1141     dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);  in aspeed_2600_smc_dma_ctrl()
1145         s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);  in aspeed_2600_smc_dma_ctrl()
1151         s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);  in aspeed_2600_smc_dma_ctrl()
1161     s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);  in aspeed_2600_smc_dma_ctrl()
1202     } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {  in aspeed_smc_write()