Lines Matching +full:0 +full:x3a000000
41 #define R_CONF (0x00 / 4)
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
58 #define R_CE_CTRL (0x04 / 4)
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
66 #define R_INTR_CTRL (0x08 / 4)
75 #define R_CE_CMD_CTRL (0x0C / 4)
77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
85 #define R_CTRL0 (0x10 / 4)
92 #define CTRL_CMD_MASK 0xff
96 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
101 #define CTRL_CMD_MODE_MASK 0x3
102 #define CTRL_READMODE 0x0
103 #define CTRL_FREADMODE 0x1
104 #define CTRL_WRITEMODE 0x2
105 #define CTRL_USERMODE 0x3
106 #define R_CTRL1 (0x14 / 4)
107 #define R_CTRL2 (0x18 / 4)
108 #define R_CTRL3 (0x1C / 4)
109 #define R_CTRL4 (0x20 / 4)
112 #define R_SEG_ADDR0 (0x30 / 4)
114 #define SEG_END_MASK 0xff
116 #define SEG_START_MASK 0xff
117 #define R_SEG_ADDR1 (0x34 / 4)
118 #define R_SEG_ADDR2 (0x38 / 4)
119 #define R_SEG_ADDR3 (0x3C / 4)
120 #define R_SEG_ADDR4 (0x40 / 4)
123 #define R_MISC_CTRL1 (0x50 / 4)
126 #define R_DUMMY_DATA (0x54 / 4)
129 #define R_FMC_WDT2_CTRL (0x64 / 4)
133 #define FMC_WDT2_CTRL_EN BIT(0)
134 #define R_FMC_WDT2_RELOAD (0x68 / 4)
135 #define R_FMC_WDT2_RESTART (0x6C / 4)
138 #define R_DMA_DRAM_ADDR_HIGH (0x7c / 4)
141 #define R_DMA_CTRL (0x80 / 4)
144 #define DMA_CTRL_DELAY_MASK 0xf
146 #define DMA_CTRL_FREQ_MASK 0xf
151 #define DMA_CTRL_ENABLE (1 << 0)
154 #define R_DMA_FLASH_ADDR (0x84 / 4)
157 #define R_DMA_DRAM_ADDR (0x88 / 4)
160 #define R_DMA_LEN (0x8C / 4)
163 #define R_DMA_CHECKSUM (0x90 / 4)
166 #define R_TIMINGS (0x94 / 4)
169 #define R_SPI_CONF (0x00 / 4)
170 #define SPI_CONF_ENABLE_W0 0
171 #define R_SPI_CTRL0 (0x4 / 4)
172 #define R_SPI_MISC_CTRL (0x10 / 4)
173 #define R_SPI_TIMINGS (0x14 / 4)
175 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
176 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
180 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
181 * 0x80000000 - 0xBFFFFFFF (AST2500)
184 * range is 0x20000000 - 0x2FFFFFFF.
187 * 0: 4 bytes
188 * 0x1FFFFFC: 32M bytes
191 * 0: 1 byte
192 * 0x1FFFFFF: 32M bytes
195 #define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf)
197 #define DMA_LENGTH(val) ((val) & 0x01FFFFFF)
200 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
202 #define SNOOP_OFF 0xFF
203 #define SNOOP_START 0x0
213 #define ASPEED_SMC_FEATURE_DMA 0x1
214 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
215 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
216 #define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08
244 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_flash_overlap()
253 aspeed_smc_error("new segment CS%d [ 0x%" in aspeed_smc_flash_overlap()
254 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " in aspeed_smc_flash_overlap()
255 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_overlap()
297 if (cs == 0 && seg.addr != asc->flash_window_base) { in aspeed_smc_flash_set_segment()
298 aspeed_smc_error("Tried to change CS0 start address to 0x%" in aspeed_smc_flash_set_segment()
313 aspeed_smc_error("Tried to change CS%d end address to 0x%" in aspeed_smc_flash_set_segment()
325 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
333 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
347 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); in aspeed_smc_flash_default_read()
348 return 0; in aspeed_smc_flash_default_read()
354 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, in aspeed_smc_flash_default_write()
388 * In read mode, the default SPI command is READ (0x3). In other in aspeed_smc_flash_cmd()
391 * TODO: add support for READ4 (0x13) on AST2600 in aspeed_smc_flash_cmd()
445 aspeed_smc_error("invalid address 0x%08x for CS%d segment : " in aspeed_smc_check_segment_addr()
446 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_check_segment_addr()
458 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; in aspeed_smc_flash_dummies()
459 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; in aspeed_smc_flash_dummies()
481 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); in aspeed_smc_flash_setup()
492 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { in aspeed_smc_flash_setup()
493 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_flash_setup()
502 uint64_t ret = 0; in aspeed_smc_flash_read()
507 for (i = 0; i < size; i++) { in aspeed_smc_flash_read()
508 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
516 for (i = 0; i < size; i++) { in aspeed_smc_flash_read()
517 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
536 READ = 0x3, READ_4 = 0x13,
537 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
538 DOR = 0x3b, DOR_4 = 0x3c,
539 QOR = 0x6b, QOR_4 = 0x6c,
540 DIOR = 0xbb, DIOR_4 = 0xbc,
541 QIOR = 0xeb, QIOR_4 = 0xec,
543 PP = 0x2, PP_4 = 0x12,
544 DPP = 0xa2,
545 QPP = 0x32, QPP_4 = 0x34,
558 return 0; in aspeed_smc_num_dummies()
584 (uint8_t) data & 0xff); in aspeed_smc_do_snoop()
590 uint8_t cmd = data & 0xff; in aspeed_smc_do_snoop()
597 if (ndummies <= 0) { in aspeed_smc_do_snoop()
608 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_do_snoop()
640 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); in aspeed_smc_flash_write()
650 for (i = 0; i < size; i++) { in aspeed_smc_flash_write()
651 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
658 for (i = 0; i < size; i++) { in aspeed_smc_flash_write()
659 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
694 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ in aspeed_smc_flash_update_ctrl()
722 memset(s->regs, 0, sizeof s->regs); in aspeed_smc_reset()
725 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_reset()
736 qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); in aspeed_smc_reset()
742 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
750 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
756 s->snoop_dummies = 0; in aspeed_smc_reset()
759 #define ASPEED_WDT_RELOAD 0x04
760 #define ASPEED_WDT_RESTART 0x08
761 #define ASPEED_WDT_CTRL 0x0C
799 value &= ~BIT(0); in aspeed_smc_wdt2_enable()
840 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", in aspeed_smc_read()
850 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 in aspeed_smc_hclk_divisor()
854 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { in aspeed_smc_hclk_divisor()
883 s->regs[s->r_timings] &= ~(0xf << hclk_shift); in aspeed_smc_dma_calibration()
893 cs = 0; in aspeed_smc_dma_calibration()
919 return (delay & 0x7) < 1; in aspeed_smc_inject_read_failure()
921 return (delay & 0x7) < 2; in aspeed_smc_inject_read_failure()
984 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; in aspeed_smc_dma_checksum()
1055 s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff; in aspeed_smc_dma_rw()
1066 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the in aspeed_smc_dma_stop()
1070 s->regs[R_DMA_CHECKSUM] = 0; in aspeed_smc_dma_stop()
1143 if (dma_ctrl == 0xAEED0000) { in aspeed_2600_smc_dma_ctrl()
1150 if (dma_ctrl == 0xDEEA0000) { in aspeed_2600_smc_dma_ctrl()
1191 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1193 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1217 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", in aspeed_smc_write()
1235 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_instance_init()
1273 hwaddr offset = 0; in aspeed_smc_realize()
1310 memory_region_add_subregion(&s->mmio_flash_container, 0x0, in aspeed_smc_realize()
1320 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_realize()
1364 DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
1414 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1445 uint32_t reg = 0; in aspeed_smc_segment_to_reg()
1459 { 0x10000000, 32 * MiB },
1476 asc->flash_window_base = 0x10000000; in aspeed_2400_smc_class_init()
1477 asc->flash_window_size = 0x6000000; in aspeed_2400_smc_class_init()
1478 asc->features = 0x0; in aspeed_2400_smc_class_init()
1501 { 0x20000000, 64 * MiB }, /* start address is readonly */
1502 { 0x24000000, 32 * MiB },
1503 { 0x26000000, 32 * MiB },
1504 { 0x28000000, 32 * MiB },
1505 { 0x2A000000, 32 * MiB }
1522 asc->segment_addr_mask = 0xffff0000; in aspeed_2400_fmc_class_init()
1524 asc->flash_window_base = 0x20000000; in aspeed_2400_fmc_class_init()
1525 asc->flash_window_size = 0x10000000; in aspeed_2400_fmc_class_init()
1527 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2400_fmc_class_init()
1528 asc->dma_dram_mask = 0x1FFFFFFC; in aspeed_2400_fmc_class_init()
1544 { 0x30000000, 64 * MiB },
1559 asc->r_ce_ctrl = 0xff; in aspeed_2400_spi1_class_init()
1566 asc->flash_window_base = 0x30000000; in aspeed_2400_spi1_class_init()
1567 asc->flash_window_size = 0x10000000; in aspeed_2400_spi1_class_init()
1568 asc->features = 0x0; in aspeed_2400_spi1_class_init()
1589 { 0x20000000, 128 * MiB }, /* start address is readonly */
1590 { 0x28000000, 32 * MiB },
1591 { 0x2A000000, 32 * MiB },
1608 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_fmc_class_init()
1610 asc->flash_window_base = 0x20000000; in aspeed_2500_fmc_class_init()
1611 asc->flash_window_size = 0x10000000; in aspeed_2500_fmc_class_init()
1613 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2500_fmc_class_init()
1614 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2500_fmc_class_init()
1630 { 0x30000000, 32 * MiB }, /* start address is readonly */
1631 { 0x32000000, 96 * MiB }, /* end address is readonly */
1648 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi1_class_init()
1649 asc->flash_window_base = 0x30000000; in aspeed_2500_spi1_class_init()
1650 asc->flash_window_size = 0x8000000; in aspeed_2500_spi1_class_init()
1651 asc->features = 0x0; in aspeed_2500_spi1_class_init()
1666 { 0x38000000, 32 * MiB }, /* start address is readonly */
1667 { 0x3A000000, 96 * MiB }, /* end address is readonly */
1684 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi2_class_init()
1685 asc->flash_window_base = 0x38000000; in aspeed_2500_spi2_class_init()
1686 asc->flash_window_size = 0x8000000; in aspeed_2500_spi2_class_init()
1687 asc->features = 0x0; in aspeed_2500_spi2_class_init()
1708 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1713 uint32_t reg = 0; in aspeed_2600_smc_segment_to_reg()
1717 return 0; in aspeed_2600_smc_segment_to_reg()
1737 seg->size = 0; in aspeed_2600_smc_reg_to_segment()
1748 { 0x0, 128 * MiB }, /* start address is readonly */
1750 { 0x0, 0 }, /* disabled */
1767 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_fmc_class_init()
1769 asc->flash_window_base = 0x20000000; in aspeed_2600_fmc_class_init()
1770 asc->flash_window_size = 0x10000000; in aspeed_2600_fmc_class_init()
1773 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_fmc_class_init()
1774 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_fmc_class_init()
1790 { 0x0, 128 * MiB }, /* start address is readonly */
1791 { 0x0, 0 }, /* disabled */
1808 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi1_class_init()
1809 asc->flash_window_base = 0x30000000; in aspeed_2600_spi1_class_init()
1810 asc->flash_window_size = 0x10000000; in aspeed_2600_spi1_class_init()
1813 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi1_class_init()
1814 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi1_class_init()
1830 { 0x0, 128 * MiB }, /* start address is readonly */
1831 { 0x0, 0 }, /* disabled */
1832 { 0x0, 0 }, /* disabled */
1849 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi2_class_init()
1850 asc->flash_window_base = 0x50000000; in aspeed_2600_spi2_class_init()
1851 asc->flash_window_size = 0x10000000; in aspeed_2600_spi2_class_init()
1854 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi2_class_init()
1855 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi2_class_init()
1874 #define AST1030_SEG_ADDR_MASK 0x0ff80000
1879 uint32_t reg = 0; in aspeed_1030_smc_segment_to_reg()
1883 return 0; in aspeed_1030_smc_segment_to_reg()
1903 seg->size = 0; in aspeed_1030_smc_reg_to_segment()
1913 { 0x0, 128 * MiB }, /* start address is readonly */
1915 { 0x0, 0 }, /* disabled */
1932 asc->segment_addr_mask = 0x0ff80ff8; in aspeed_1030_fmc_class_init()
1934 asc->flash_window_base = 0x80000000; in aspeed_1030_fmc_class_init()
1935 asc->flash_window_size = 0x10000000; in aspeed_1030_fmc_class_init()
1937 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_fmc_class_init()
1938 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_fmc_class_init()
1954 { 0x0, 128 * MiB }, /* start address is readonly */
1955 { 0x0, 0 }, /* disabled */
1972 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi1_class_init()
1973 asc->flash_window_base = 0x90000000; in aspeed_1030_spi1_class_init()
1974 asc->flash_window_size = 0x10000000; in aspeed_1030_spi1_class_init()
1976 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi1_class_init()
1977 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi1_class_init()
1992 { 0x0, 128 * MiB }, /* start address is readonly */
1993 { 0x0, 0 }, /* disabled */
2010 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi2_class_init()
2011 asc->flash_window_base = 0xb0000000; in aspeed_1030_spi2_class_init()
2012 asc->flash_window_size = 0x10000000; in aspeed_1030_spi2_class_init()
2014 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi2_class_init()
2015 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi2_class_init()
2034 #define AST2700_SEG_ADDR_MASK 0xffff0000
2039 uint32_t reg = 0; in aspeed_2700_smc_segment_to_reg()
2043 return 0; in aspeed_2700_smc_segment_to_reg()
2063 seg->size = 0; in aspeed_2700_smc_reg_to_segment()
2070 [R_CE_CTRL] = 0x0000aa00,
2071 [R_CTRL0] = 0x406b0641,
2072 [R_CTRL1] = 0x00000400,
2073 [R_CTRL2] = 0x00000400,
2074 [R_CTRL3] = 0x00000400,
2075 [R_SEG_ADDR0] = 0x08000000,
2076 [R_SEG_ADDR1] = 0x10000800,
2077 [R_SEG_ADDR2] = 0x00000000,
2078 [R_SEG_ADDR3] = 0x00000000,
2079 [R_DUMMY_DATA] = 0x00010000,
2080 [R_DMA_DRAM_ADDR_HIGH] = 0x00000000,
2081 [R_TIMINGS] = 0x007b0000,
2095 { 0x0, 128 * MiB }, /* start address is readonly */
2098 { 0x0, 0 }, /* disabled */
2115 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_fmc_class_init()
2117 asc->flash_window_base = 0x100000000; in aspeed_2700_fmc_class_init()
2121 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_fmc_class_init()
2122 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_fmc_class_init()
2138 { 0x0, 128 * MiB }, /* start address is readonly */
2140 { 0x0, 0 }, /* disabled */
2157 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi0_class_init()
2158 asc->flash_window_base = 0x180000000; in aspeed_2700_spi0_class_init()
2162 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi0_class_init()
2163 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi0_class_init()
2179 { 0x0, 128 * MiB }, /* start address is readonly */
2180 { 0x0, 0 }, /* disabled */
2197 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi1_class_init()
2198 asc->flash_window_base = 0x200000000; in aspeed_2700_spi1_class_init()
2202 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi1_class_init()
2203 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi1_class_init()
2219 { 0x0, 128 * MiB }, /* start address is readonly */
2220 { 0x0, 0 }, /* disabled */
2237 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi2_class_init()
2238 asc->flash_window_base = 0x280000000; in aspeed_2700_spi2_class_init()
2242 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2700_spi2_class_init()
2243 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi2_class_init()