Lines Matching +full:fu540 +full:- +full:c000 +full:- +full:ccache
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
128 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); in create_fdt()
129 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); in create_fdt()
130 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); in create_fdt()
136 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); in create_fdt()
137 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", in create_fdt()
139 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); in create_fdt()
140 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
147 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); in create_fdt()
148 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", in create_fdt()
150 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); in create_fdt()
151 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
164 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", in create_fdt()
166 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
167 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
169 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { in create_fdt()
172 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); in create_fdt()
177 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); in create_fdt()
179 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); in create_fdt()
181 riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename); in create_fdt()
183 riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); in create_fdt()
191 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); in create_fdt()
192 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); in create_fdt()
193 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); in create_fdt()
198 cells = g_new0(uint32_t, ms->smp.cpus * 4); in create_fdt()
199 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt()
201 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); in create_fdt()
217 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", in create_fdt()
218 cells, ms->smp.cpus * sizeof(uint32_t) * 4); in create_fdt()
225 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); in create_fdt()
230 "sifive,fu540-c000-otp"); in create_fdt()
234 nodename = g_strdup_printf("/soc/clock-controller@%lx", in create_fdt()
238 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); in create_fdt()
245 "sifive,fu540-c000-prci"); in create_fdt()
249 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); in create_fdt()
250 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt()
252 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); in create_fdt()
254 /* cpu 0 is the management hart that does not have S-mode */ in create_fdt()
259 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); in create_fdt()
260 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); in create_fdt()
266 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", in create_fdt()
269 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); in create_fdt()
272 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); in create_fdt()
273 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", in create_fdt()
274 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); in create_fdt()
279 SIFIVE_U_PLIC_NUM_SOURCES - 1); in create_fdt()
292 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); in create_fdt()
293 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); in create_fdt()
294 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); in create_fdt()
295 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); in create_fdt()
305 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
309 nodename = g_strdup_printf("/gpio-restart"); in create_fdt()
312 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); in create_fdt()
318 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); in create_fdt()
323 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
328 "sifive,fu540-c000-pdma"); in create_fdt()
331 nodename = g_strdup_printf("/soc/cache-controller@%lx", in create_fdt()
339 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
340 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); in create_fdt()
341 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); in create_fdt()
342 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); in create_fdt()
343 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); in create_fdt()
344 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); in create_fdt()
346 "sifive,fu540-c000-ccache"); in create_fdt()
352 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
353 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); in create_fdt()
357 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
367 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); in create_fdt()
368 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); in create_fdt()
369 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); in create_fdt()
371 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); in create_fdt()
377 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
378 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); in create_fdt()
382 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
392 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); in create_fdt()
393 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); in create_fdt()
394 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); in create_fdt()
395 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); in create_fdt()
397 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); in create_fdt()
405 "sifive,fu540-c000-gem"); in create_fdt()
411 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); in create_fdt()
412 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); in create_fdt()
413 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); in create_fdt()
414 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
418 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", in create_fdt()
420 qemu_fdt_setprop(fdt, nodename, "local-mac-address", in create_fdt()
421 s->soc.gem.conf.macaddr.a, ETH_ALEN); in create_fdt()
422 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); in create_fdt()
423 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); in create_fdt()
430 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", in create_fdt()
444 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
450 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
460 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
466 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
478 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
493 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); in create_fdt()
497 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); in create_fdt()
530 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); in sifive_u_machine_init()
531 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, in sifive_u_machine_init()
533 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, in sifive_u_machine_init()
535 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in sifive_u_machine_init()
539 machine->ram); in sifive_u_machine_init()
547 /* register gpio-restart */ in sifive_u_machine_init()
548 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, in sifive_u_machine_init()
552 if (machine->dtb) { in sifive_u_machine_init()
553 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); in sifive_u_machine_init()
554 if (!machine->fdt) { in sifive_u_machine_init()
559 create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); in sifive_u_machine_init()
562 if (s->start_in_flash) { in sifive_u_machine_init()
564 * If start_in_flash property is given, assign s->msel to a value in sifive_u_machine_init()
565 * that representing booting from QSPI0 memory-mapped flash. in sifive_u_machine_init()
573 s->msel = MSEL_MEMMAP_QSPI0_FLASH; in sifive_u_machine_init()
576 switch (s->msel) { in sifive_u_machine_init()
589 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); in sifive_u_machine_init()
593 if (machine->kernel_filename) { in sifive_u_machine_init()
594 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, in sifive_u_machine_init()
597 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, in sifive_u_machine_init()
610 riscv_load_fdt(fdt_load_addr, machine->fdt); in sifive_u_machine_init()
612 if (!riscv_is_32bit(&s->soc.u_cpus)) { in sifive_u_machine_init()
618 s->msel, /* MSEL pin state */ in sifive_u_machine_init()
632 if (riscv_is_32bit(&s->soc.u_cpus)) { in sifive_u_machine_init()
648 riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus, in sifive_u_machine_init()
661 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); in sifive_u_machine_init()
664 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); in sifive_u_machine_init()
667 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); in sifive_u_machine_init()
670 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); in sifive_u_machine_init()
677 qdev_get_child_bus(sd_dev, "sd-bus"), in sifive_u_machine_init()
685 return s->start_in_flash; in sifive_u_machine_get_start_in_flash()
692 s->start_in_flash = value; in sifive_u_machine_set_start_in_flash()
699 s->start_in_flash = false; in sifive_u_machine_instance_init()
700 s->msel = 0; in sifive_u_machine_instance_init()
701 object_property_add_uint32_ptr(obj, "msel", &s->msel, in sifive_u_machine_instance_init()
706 s->serial = OTP_SERIAL; in sifive_u_machine_instance_init()
707 object_property_add_uint32_ptr(obj, "serial", &s->serial, in sifive_u_machine_instance_init()
716 mc->desc = "RISC-V Board compatible with SiFive U SDK"; in sifive_u_machine_class_init()
717 mc->init = sifive_u_machine_init; in sifive_u_machine_class_init()
718 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; in sifive_u_machine_class_init()
719 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; in sifive_u_machine_class_init()
720 mc->default_cpu_type = SIFIVE_U_CPU; in sifive_u_machine_class_init()
721 mc->default_cpus = mc->min_cpus; in sifive_u_machine_class_init()
722 mc->default_ram_id = "riscv.sifive.u.ram"; in sifive_u_machine_class_init()
724 object_class_property_add_bool(oc, "start-in-flash", in sifive_u_machine_class_init()
727 object_class_property_set_description(oc, "start-in-flash", in sifive_u_machine_class_init()
752 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); in type_init()
753 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); in type_init()
755 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, in type_init()
757 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); in type_init()
758 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); in type_init()
759 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); in type_init()
760 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); in type_init()
762 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); in type_init()
763 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); in type_init()
765 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, in type_init()
768 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); in type_init()
769 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); in type_init()
770 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); in type_init()
771 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); in type_init()
772 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); in type_init()
773 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); in type_init()
774 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); in type_init()
775 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); in type_init()
776 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); in type_init()
790 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); in sifive_u_soc_realize()
791 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); in sifive_u_soc_realize()
792 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); in sifive_u_soc_realize()
793 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); in sifive_u_soc_realize()
795 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); in sifive_u_soc_realize()
796 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); in sifive_u_soc_realize()
798 * The cluster must be realized after the RISC-V hart array container, in sifive_u_soc_realize()
803 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); in sifive_u_soc_realize()
804 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); in sifive_u_soc_realize()
813 * Add L2-LIM at reset size. in sifive_u_soc_realize()
827 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); in sifive_u_soc_realize()
830 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, in sifive_u_soc_realize()
831 plic_hart_config, ms->smp.cpus, 0, in sifive_u_soc_realize()
843 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); in sifive_u_soc_realize()
845 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); in sifive_u_soc_realize()
847 ms->smp.cpus, false); in sifive_u_soc_realize()
850 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in sifive_u_soc_realize()
854 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { in sifive_u_soc_realize()
857 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); in sifive_u_soc_realize()
859 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); in sifive_u_soc_realize()
860 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { in sifive_u_soc_realize()
863 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); in sifive_u_soc_realize()
866 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); in sifive_u_soc_realize()
870 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, in sifive_u_soc_realize()
871 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
876 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); in sifive_u_soc_realize()
877 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); in sifive_u_soc_realize()
881 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, in sifive_u_soc_realize()
882 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
886 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); in sifive_u_soc_realize()
887 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { in sifive_u_soc_realize()
890 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); in sifive_u_soc_realize()
892 qemu_configure_nic_device(DEVICE(&s->gem), true, NULL); in sifive_u_soc_realize()
893 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, in sifive_u_soc_realize()
895 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { in sifive_u_soc_realize()
898 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); in sifive_u_soc_realize()
899 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, in sifive_u_soc_realize()
900 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); in sifive_u_soc_realize()
904 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { in sifive_u_soc_realize()
907 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, in sifive_u_soc_realize()
912 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, in sifive_u_soc_realize()
913 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
918 create_unimplemented_device("riscv.sifive.u.gem-mgmt", in sifive_u_soc_realize()
927 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); in sifive_u_soc_realize()
928 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, in sifive_u_soc_realize()
930 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, in sifive_u_soc_realize()
931 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); in sifive_u_soc_realize()
932 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); in sifive_u_soc_realize()
933 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, in sifive_u_soc_realize()
935 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, in sifive_u_soc_realize()
936 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); in sifive_u_soc_realize()
941 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
950 dc->realize = sifive_u_soc_realize; in sifive_u_soc_class_init()
952 dc->user_creatable = false; in sifive_u_soc_class_init()