12  * 2) PLIC (Platform Level Interrupt Controller)
111         "sifive,plic-1.0.0", "riscv,plic0"  in create_fdt()
831     /* create PLIC hart topology configuration string */  in sifive_u_soc_realize()
835     s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,  in sifive_u_soc_realize()
848         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));  in sifive_u_soc_realize()
850         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));  in sifive_u_soc_realize()
873     /* Connect GPIO interrupts to the PLIC */  in sifive_u_soc_realize()
876                            qdev_get_gpio_in(DEVICE(s->plic),  in sifive_u_soc_realize()
884     /* Connect PDMA interrupts to the PLIC */  in sifive_u_soc_realize()
887                            qdev_get_gpio_in(DEVICE(s->plic),  in sifive_u_soc_realize()
905                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));  in sifive_u_soc_realize()
915         /* Connect PWM interrupts to the PLIC */  in sifive_u_soc_realize()
918                                qdev_get_gpio_in(DEVICE(s->plic),  in sifive_u_soc_realize()
936                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));  in sifive_u_soc_realize()
941                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));  in sifive_u_soc_realize()