hw/riscv/riscv-iommu-bits.h

19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
37 #define RISCV_IOMMU_FQ_HDR_DID          GENMASK_ULL(63, 40)
52 #define RISCV_IOMMU_PREQ_HDR_DID        GENMASK_ULL(63, 40)
60 #define RISCV_IOMMU_PREQ_UADDR          GENMASK_ULL(63, 12)
73 #define RISCV_IOMMU_ATP_MODE_FIELD      GENMASK_ULL(63, 60)
214 #define RISCV_IOMMU_IOHPMCYCLES_OVF     BIT_ULL(63)
232 #define RISCV_IOMMU_IOHPMEVT_OF         BIT_ULL(63)
255 #define RISCV_IOMMU_TR_REQ_CTL_DID      GENMASK_ULL(63, 40)
345 #define RISCV_IOMMU_CMD_IOFENCE_DATA    GENMASK_ULL(63, 32)
352 #define RISCV_IOMMU_CMD_IODIR_DID       GENMASK_ULL(63, 40)
362 #define RISCV_IOMMU_CMD_ATS_DSEG        GENMASK_ULL(63, 56)
424 #define RISCV_IOMMU_PC_TA_RESERVED      GENMASK_ULL(63, 32)
461 #define RISCV_IOMMU_MSI_PTE_C           BIT_ULL(63)