hw/riscv/riscv-iommu-bits.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright © 2022-2023 Rivos Inc.
4  * Copyright © 2023 FORTH-ICS/CARV
5  * Copyright © 2023 RISC-V IOMMU Task Group
7  * RISC-V IOMMU - Register Layout and Data Structures.
10  * https://github.com/riscv-non-isa/riscv-iommu
16 #define RISCV_IOMMU_SPEC_DOT_VER 0x010
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23  * struct riscv_iommu_fq_record - Fault/Event Queue Record
33 #define RISCV_IOMMU_FQ_HDR_CAUSE        GENMASK_ULL(11, 0)
37 #define RISCV_IOMMU_FQ_HDR_DID          GENMASK_ULL(63, 40)
40  * struct riscv_iommu_pq_record - PCIe Page Request record
52 #define RISCV_IOMMU_PREQ_HDR_DID        GENMASK_ULL(63, 40)
55 #define RISCV_IOMMU_PREQ_PAYLOAD_R      BIT_ULL(0)
58 #define RISCV_IOMMU_PREQ_PAYLOAD_M      GENMASK_ULL(2, 0)
60 #define RISCV_IOMMU_PREQ_UADDR          GENMASK_ULL(63, 12)
64 #define RISCV_IOMMU_QUEUE_LOGSZ_FIELD   GENMASK_ULL(4, 0)
65 #define RISCV_IOMMU_QUEUE_INDEX_FIELD   GENMASK_ULL(31, 0)
66 #define RISCV_IOMMU_QUEUE_ENABLE        BIT(0)
72 #define RISCV_IOMMU_ATP_PPN_FIELD       GENMASK_ULL(43, 0)
73 #define RISCV_IOMMU_ATP_MODE_FIELD      GENMASK_ULL(63, 60)
76 #define RISCV_IOMMU_REG_CAP             0x0000
77 #define RISCV_IOMMU_CAP_VERSION         GENMASK_ULL(7, 0)
99     RISCV_IOMMU_CAP_IGS_MSI = 0,
105 #define RISCV_IOMMU_REG_FCTL            0x0008
106 #define RISCV_IOMMU_FCTL_BE             BIT(0)
110 /* 5.5 Device-directory-table pointer (64bits) */
111 #define RISCV_IOMMU_REG_DDTP            0x0010
112 #define RISCV_IOMMU_DDTP_MODE           GENMASK_ULL(3, 0)
117     RISCV_IOMMU_DDTP_MODE_OFF = 0,
126 #define RISCV_IOMMU_REG_CQB             0x0018
131 #define RISCV_IOMMU_REG_CQH             0x0020
134 #define RISCV_IOMMU_REG_CQT             0x0024
137 #define RISCV_IOMMU_REG_FQB             0x0028
142 #define RISCV_IOMMU_REG_FQH             0x0030
145 #define RISCV_IOMMU_REG_FQT             0x0034
148 #define RISCV_IOMMU_REG_PQB             0x0038
153 #define RISCV_IOMMU_REG_PQH             0x0040
156 #define RISCV_IOMMU_REG_PQT             0x0044
159 #define RISCV_IOMMU_REG_CQCSR           0x0048
170 #define RISCV_IOMMU_REG_FQCSR           0x004C
179 #define RISCV_IOMMU_REG_PQCSR           0x0050
188 #define RISCV_IOMMU_REG_IPSR            0x0054
189 #define RISCV_IOMMU_IPSR_CIP            BIT(0)
204 #define RISCV_IOMMU_REG_IOCOUNTOVF      0x0058
205 #define RISCV_IOMMU_IOCOUNTOVF_CY       BIT(0)
208 #define RISCV_IOMMU_REG_IOCOUNTINH      0x005C
209 #define RISCV_IOMMU_IOCOUNTINH_CY       BIT(0)
212 #define RISCV_IOMMU_REG_IOHPMCYCLES     0x0060
213 #define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0)
214 #define RISCV_IOMMU_IOHPMCYCLES_OVF     BIT_ULL(63)
217 #define RISCV_IOMMU_REG_IOHPMCTR_BASE   0x0068
219     (RISCV_IOMMU_REG_IOHPMCTR_BASE + (_n * 0x8))
222 #define RISCV_IOMMU_REG_IOHPMEVT_BASE   0x0160
224     (RISCV_IOMMU_REG_IOHPMEVT_BASE + (_n * 0x8))
225 #define RISCV_IOMMU_IOHPMEVT_EVENT_ID   GENMASK_ULL(14, 0)
232 #define RISCV_IOMMU_IOHPMEVT_OF         BIT_ULL(63)
235     RISCV_IOMMU_HPMEVENT_INVALID    = 0,
248 #define RISCV_IOMMU_REG_TR_REQ_IOVA     0x0258
251 #define RISCV_IOMMU_REG_TR_REQ_CTL      0x0260
252 #define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY  BIT_ULL(0)
255 #define RISCV_IOMMU_TR_REQ_CTL_DID      GENMASK_ULL(63, 40)
258 #define RISCV_IOMMU_REG_TR_RESPONSE     0x0268
259 #define RISCV_IOMMU_TR_RESPONSE_FAULT   BIT_ULL(0)
264 #define RISCV_IOMMU_REG_ICVEC           0x02F8
265 #define RISCV_IOMMU_ICVEC_CIV           GENMASK_ULL(3, 0)
271 #define RISCV_IOMMU_REG_MSI_CONFIG      0x0300
273 #define RISCV_IOMMU_REG_SIZE            0x1000
275 #define RISCV_IOMMU_DDTE_VALID          BIT_ULL(0)
278 /* Struct riscv_iommu_dc - Device Context - section 2.1 */
291 #define RISCV_IOMMU_DC_TC_V             BIT_ULL(0)
304 /* Second-stage (aka G-stage) context fields */
310     RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
320 /* First-stage context fields */
324 /* Generic I/O MMU command structure - check section 3.1 */
330 #define RISCV_IOMMU_CMD_OPCODE          GENMASK_ULL(6, 0)
334 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA       0
343 #define RISCV_IOMMU_CMD_IOFENCE_FUNC_C          0
345 #define RISCV_IOMMU_CMD_IOFENCE_DATA    GENMASK_ULL(63, 32)
348 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT    0
352 #define RISCV_IOMMU_CMD_IODIR_DID       GENMASK_ULL(63, 40)
356 #define RISCV_IOMMU_CMD_ATS_FUNC_INVAL          0
362 #define RISCV_IOMMU_CMD_ATS_DSEG        GENMASK_ULL(63, 56)
369     RISCV_IOMMU_DC_FSC_MODE_BARE = 0,
415 #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF  0
419 #define RISCV_IOMMU_PDTE_VALID          BIT_ULL(0)
423 #define RISCV_IOMMU_PC_TA_V             BIT_ULL(0)
424 #define RISCV_IOMMU_PC_TA_RESERVED      GENMASK_ULL(63, 32)
431     RISCV_IOMMU_FQ_TTYPE_NONE = 0,
443  * struct riscv_iommu_msi_pte - MSI Page Table Entry
451 #define RISCV_IOMMU_MSI_PTE_V           BIT_ULL(0)
461 #define RISCV_IOMMU_MSI_PTE_C           BIT_ULL(63)
464 #define RISCV_IOMMU_MSI_MRIF_NID        GENMASK_ULL(9, 0)