37 bool riscv_is_32bit(RISCVHartArrayState *harts)  in riscv_is_32bit()  argument
39     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);  in riscv_is_32bit()
70 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,  in riscv_calc_kernel_start_addr()  argument
72     if (riscv_is_32bit(harts)) {  in riscv_calc_kernel_start_addr()
79 const char *riscv_default_firmware_name(RISCVHartArrayState *harts)  in riscv_default_firmware_name()  argument
81     if (riscv_is_32bit(harts)) {  in riscv_default_firmware_name()
219                                RISCVHartArrayState *harts,  in riscv_load_kernel()  argument
263     if (riscv_is_32bit(harts)) {  in riscv_load_kernel()
347                                   RISCVHartArrayState *harts,  in riscv_rom_copy_firmware_info()  argument
356     if (riscv_is_32bit(harts)) {  in riscv_rom_copy_firmware_info()
385                            riscv_is_32bit(harts) ?  in riscv_rom_copy_firmware_info()
392 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,  in riscv_setup_rom_reset_vec()  argument
402     if (!riscv_is_32bit(harts)) {  in riscv_setup_rom_reset_vec()
420     if (riscv_is_32bit(harts)) {  in riscv_setup_rom_reset_vec()
428     if (!harts->harts[0].cfg.ext_zicsr) {  in riscv_setup_rom_reset_vec()
443     riscv_rom_copy_firmware_info(machine, harts,  in riscv_setup_rom_reset_vec()