111 static void sdram_bank_map(Ppc4xxSdramBank *bank)  in sdram_bank_map()  argument
113     trace_ppc4xx_sdram_map(bank->base, bank->size);  in sdram_bank_map()
114     memory_region_init(&bank->container, NULL, "sdram-container", bank->size);  in sdram_bank_map()
115     memory_region_add_subregion(&bank->container, 0, &bank->ram);  in sdram_bank_map()
116     memory_region_add_subregion(get_system_memory(), bank->base,  in sdram_bank_map()
117                                 &bank->container);  in sdram_bank_map()
120 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)  in sdram_bank_unmap()  argument
122     trace_ppc4xx_sdram_unmap(bank->base, bank->size);  in sdram_bank_unmap()
123     memory_region_del_subregion(get_system_memory(), &bank->container);  in sdram_bank_unmap()
124     memory_region_del_subregion(&bank->container, &bank->ram);  in sdram_bank_unmap()
125     object_unparent(OBJECT(&bank->container));  in sdram_bank_unmap()
128 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,  in sdram_bank_set_bcr()  argument
131     if (memory_region_is_mapped(&bank->container)) {  in sdram_bank_set_bcr()
132         sdram_bank_unmap(bank);  in sdram_bank_set_bcr()
134     bank->bcr = bcr;  in sdram_bank_set_bcr()
135     bank->base = base;  in sdram_bank_set_bcr()
136     bank->size = size;  in sdram_bank_set_bcr()
138         sdram_bank_map(bank);  in sdram_bank_set_bcr()
238             ret = s->bank[0].bcr;  in sdram_ddr_dcr_read()
241             ret = s->bank[1].bcr;  in sdram_ddr_dcr_read()
244             ret = s->bank[2].bcr;  in sdram_ddr_dcr_read()
247             ret = s->bank[3].bcr;  in sdram_ddr_dcr_read()
298                     if (s->bank[i].size) {  in sdram_ddr_dcr_write()
299                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr_dcr_write()
300                                            s->bank[i].base, s->bank[i].size,  in sdram_ddr_dcr_write()
309                     if (s->bank[i].size) {  in sdram_ddr_dcr_write()
310                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr_dcr_write()
311                                            s->bank[i].base, s->bank[i].size,  in sdram_ddr_dcr_write()
339             if (s->bank[i].size) {  in sdram_ddr_dcr_write()
340                 sdram_bank_set_bcr(&s->bank[i], val,  in sdram_ddr_dcr_write()
403     if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,  in ppc4xx_sdram_ddr_realize()
408         if (s->bank[i].size) {  in ppc4xx_sdram_ddr_realize()
409             s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);  in ppc4xx_sdram_ddr_realize()
410             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in ppc4xx_sdram_ddr_realize()
411                                s->bank[i].base, s->bank[i].size, 0);  in ppc4xx_sdram_ddr_realize()
413             sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);  in ppc4xx_sdram_ddr_realize()
415         trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),  in ppc4xx_sdram_ddr_realize()
416                                 sdram_ddr_size(s->bank[i].bcr),  in ppc4xx_sdram_ddr_realize()
417                                 s->bank[i].bcr);  in ppc4xx_sdram_ddr_realize()
536         if (s->bank[dcrn - SDRAM_R0BAS].size) {  in sdram_ddr2_dcr_read()
537             ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,  in sdram_ddr2_dcr_read()
538                                  s->bank[dcrn - SDRAM_R0BAS].size);  in sdram_ddr2_dcr_read()
610                     if (s->bank[i].size) {  in sdram_ddr2_dcr_write()
611                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr2_dcr_write()
612                                            s->bank[i].base, s->bank[i].size,  in sdram_ddr2_dcr_write()
622                     if (s->bank[i].size) {  in sdram_ddr2_dcr_write()
623                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr2_dcr_write()
624                                            s->bank[i].base, s->bank[i].size,  in sdram_ddr2_dcr_write()
670     if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,  in ppc4xx_sdram_ddr2_realize()
675         if (s->bank[i].size) {  in ppc4xx_sdram_ddr2_realize()
676             s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);  in ppc4xx_sdram_ddr2_realize()
677             s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;  in ppc4xx_sdram_ddr2_realize()
678             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in ppc4xx_sdram_ddr2_realize()
679                                s->bank[i].base, s->bank[i].size, 0);  in ppc4xx_sdram_ddr2_realize()
681             sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);  in ppc4xx_sdram_ddr2_realize()
683         trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),  in ppc4xx_sdram_ddr2_realize()
684                                 sdram_ddr2_size(s->bank[i].bcr),  in ppc4xx_sdram_ddr2_realize()
685                                 s->bank[i].bcr);  in ppc4xx_sdram_ddr2_realize()