Lines Matching +full:b +full:- +full:facing
19 #include "hw/ppc/e500-ccsr.h"
20 #include "hw/qdev-properties.h"
25 #include "hw/pci-host/ppce500.h"
38 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
46 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
47 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
49 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
50 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
51 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
52 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
54 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
71 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
92 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
115 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
145 value = pci->pob[idx].potar; in pci_reg_read4()
148 value = pci->pob[idx].potear; in pci_reg_read4()
151 value = pci->pob[idx].powbar; in pci_reg_read4()
154 value = pci->pob[idx].powar; in pci_reg_read4()
164 idx = ((addr >> 5) & 0x3) - 1; in pci_reg_read4()
167 value = pci->pib[idx].pitar; in pci_reg_read4()
170 value = pci->pib[idx].piwbar; in pci_reg_read4()
173 value = pci->pib[idx].piwbear; in pci_reg_read4()
176 value = pci->pib[idx].piwar; in pci_reg_read4()
184 value = pci->gasket_time; in pci_reg_read4()
191 pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__, in pci_reg_read4()
199 uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; in e500_update_piw()
200 uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; in e500_update_piw()
201 uint64_t war = pci->pib[idx].piwar; in e500_update_piw()
204 MemoryRegion *mem = &pci->pib[idx].mem; in e500_update_piw()
205 MemoryRegion *bm = &pci->bm; in e500_update_piw()
222 memory_region_add_subregion_overlap(bm, wbar, mem, -1); in e500_update_piw()
232 uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; in e500_update_pow()
233 uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; in e500_update_pow()
234 uint64_t war = pci->pob[idx].powar; in e500_update_pow()
236 MemoryRegion *mem = &pci->pob[idx].mem; in e500_update_pow()
252 memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, in e500_update_pow()
270 pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n", in pci_reg_write4()
281 pci->pob[idx].potar = value; in pci_reg_write4()
285 pci->pob[idx].potear = value; in pci_reg_write4()
289 pci->pob[idx].powbar = value; in pci_reg_write4()
293 pci->pob[idx].powar = value; in pci_reg_write4()
304 idx = ((addr >> 5) & 0x3) - 1; in pci_reg_write4()
307 pci->pib[idx].pitar = value; in pci_reg_write4()
311 pci->pib[idx].piwbar = value; in pci_reg_write4()
315 pci->pib[idx].piwbear = value; in pci_reg_write4()
319 pci->pib[idx].piwar = value; in pci_reg_write4()
328 pci->gasket_time = value; in pci_reg_write4()
344 int devno = PCI_SLOT(pci_dev->devfn); in mpc85xx_pci_map_irq()
349 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, in mpc85xx_pci_map_irq()
350 pci_dev->devfn, pin, ret, devno); in mpc85xx_pci_map_irq()
358 qemu_irq *pic = s->irq; in mpc85xx_pci_set_irq()
371 route.irq = s->irq_num[pin]; in e500_route_intx_pin_to_irq()
373 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); in e500_route_intx_pin_to_irq()
420 PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); in e500_pcihost_bridge_realize() local
422 "/e500-ccsr")); in e500_pcihost_bridge_realize()
424 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, in e500_pcihost_bridge_realize()
425 0, int128_get64(ccsr->ccsr_space.size)); in e500_pcihost_bridge_realize()
426 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); in e500_pcihost_bridge_realize()
434 return &s->bm_as; in e500_pcihost_set_iommu()
446 PCIBus *b; in e500_pcihost_realize() local
452 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { in e500_pcihost_realize()
453 sysbus_init_irq(sbd, &s->irq[i]); in e500_pcihost_realize()
457 s->irq_num[i] = s->first_pin_irq + i; in e500_pcihost_realize()
460 memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); in e500_pcihost_realize()
461 memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); in e500_pcihost_realize()
464 memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); in e500_pcihost_realize()
466 b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq, in e500_pcihost_realize()
467 mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, in e500_pcihost_realize()
468 PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); in e500_pcihost_realize()
469 h->bus = b; in e500_pcihost_realize()
472 memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); in e500_pcihost_realize()
473 memory_region_add_subregion(&s->bm, 0x0, &s->busmem); in e500_pcihost_realize()
474 address_space_init(&s->bm_as, &s->bm, "pci-bm"); in e500_pcihost_realize()
475 pci_setup_iommu(b, &ppce500_iommu_ops, s); in e500_pcihost_realize()
477 pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE); in e500_pcihost_realize()
479 memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); in e500_pcihost_realize()
480 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, in e500_pcihost_realize()
481 "pci-conf-idx", 4); in e500_pcihost_realize()
482 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, in e500_pcihost_realize()
483 "pci-conf-data", 4); in e500_pcihost_realize()
484 memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, in e500_pcihost_realize()
486 memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); in e500_pcihost_realize()
487 memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); in e500_pcihost_realize()
488 memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); in e500_pcihost_realize()
489 sysbus_init_mmio(sbd, &s->container); in e500_pcihost_realize()
490 pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); in e500_pcihost_realize()
498 k->realize = e500_pcihost_bridge_realize; in e500_host_bridge_class_init()
499 k->vendor_id = PCI_VENDOR_ID_FREESCALE; in e500_host_bridge_class_init()
500 k->device_id = PCI_DEVICE_ID_MPC8533E; in e500_host_bridge_class_init()
501 k->class_id = PCI_CLASS_PROCESSOR_POWERPC; in e500_host_bridge_class_init()
502 dc->desc = "Host bridge"; in e500_host_bridge_class_init()
504 * PCI-facing part of the host bridge, not usable without the in e500_host_bridge_class_init()
505 * host-facing part, which can't be device_add'ed, yet. in e500_host_bridge_class_init()
507 dc->user_creatable = false; in e500_host_bridge_class_init()
520 dc->realize = e500_pcihost_realize; in e500_pcihost_class_init()
521 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in e500_pcihost_class_init()
523 dc->vmsd = &vmstate_ppce500_pci; in e500_pcihost_class_init()