Lines Matching +full:bm +full:- +full:work

2  * Emulation of the ibm,plb-pcix PCI controller
5 * Copyright (c) 2016-2018 BALATON Zoltan
7 * Derived from ppc4xx_pci.c and pci-host/ppce500.c
23 #include "qemu/error-report.h"
28 #include "hw/pci-host/ppc4xx.h"
61 MemoryRegion bm; member
115 MemoryRegion *mem = &s->pim[idx].mr; in ppc440_pcix_update_pim()
120 ppc440_pcix_clear_region(&s->bm, mem); in ppc440_pcix_update_pim()
122 if (!(s->pim[idx].sa & 1)) { in ppc440_pcix_update_pim()
128 size = ~(s->pim[idx].sa & ~7ULL) + 1; in ppc440_pcix_update_pim()
130 s->pim[idx].la, size); in ppc440_pcix_update_pim()
131 memory_region_add_subregion_overlap(&s->bm, 0, mem, -1); in ppc440_pcix_update_pim()
134 trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la); in ppc440_pcix_update_pim()
140 MemoryRegion *mem = &s->pom[idx].mr; in ppc440_pcix_update_pom()
148 if (!(s->pom[idx].sa & 1)) { in ppc440_pcix_update_pom()
154 size = ~(s->pom[idx].sa & 0xfffffffe) + 1; in ppc440_pcix_update_pom()
158 memory_region_init_alias(mem, OBJECT(s), name, &s->busmem, in ppc440_pcix_update_pom()
159 s->pom[idx].pcia, size); in ppc440_pcix_update_pom()
160 memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem); in ppc440_pcix_update_pom()
163 trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia); in ppc440_pcix_update_pom()
174 stl_le_p(s->config + addr, val); in ppc440_pcix_reg_write4()
178 s->pom[0].la &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
179 s->pom[0].la |= val; in ppc440_pcix_reg_write4()
183 s->pom[0].la &= 0xffffffffULL; in ppc440_pcix_reg_write4()
184 s->pom[0].la |= val << 32; in ppc440_pcix_reg_write4()
188 s->pom[0].sa = val; in ppc440_pcix_reg_write4()
192 s->pom[0].pcia &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
193 s->pom[0].pcia |= val; in ppc440_pcix_reg_write4()
197 s->pom[0].pcia &= 0xffffffffULL; in ppc440_pcix_reg_write4()
198 s->pom[0].pcia |= val << 32; in ppc440_pcix_reg_write4()
202 s->pom[1].la &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
203 s->pom[1].la |= val; in ppc440_pcix_reg_write4()
207 s->pom[1].la &= 0xffffffffULL; in ppc440_pcix_reg_write4()
208 s->pom[1].la |= val << 32; in ppc440_pcix_reg_write4()
212 s->pom[1].sa = val; in ppc440_pcix_reg_write4()
216 s->pom[1].pcia &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
217 s->pom[1].pcia |= val; in ppc440_pcix_reg_write4()
221 s->pom[1].pcia &= 0xffffffffULL; in ppc440_pcix_reg_write4()
222 s->pom[1].pcia |= val << 32; in ppc440_pcix_reg_write4()
226 s->pom[2].sa = val; in ppc440_pcix_reg_write4()
230 s->pim[0].sa &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
231 s->pim[0].sa |= val; in ppc440_pcix_reg_write4()
235 s->pim[0].la &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
236 s->pim[0].la |= val; in ppc440_pcix_reg_write4()
240 s->pim[0].la &= 0xffffffffULL; in ppc440_pcix_reg_write4()
241 s->pim[0].la |= val << 32; in ppc440_pcix_reg_write4()
245 s->pim[1].sa = val; in ppc440_pcix_reg_write4()
249 s->pim[1].la &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
250 s->pim[1].la |= val; in ppc440_pcix_reg_write4()
254 s->pim[1].la &= 0xffffffffULL; in ppc440_pcix_reg_write4()
255 s->pim[1].la |= val << 32; in ppc440_pcix_reg_write4()
259 s->pim[2].sa &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
260 s->pim[2].sa |= val; in ppc440_pcix_reg_write4()
264 s->pim[2].la &= 0xffffffff00000000ULL; in ppc440_pcix_reg_write4()
265 s->pim[2].la |= val; in ppc440_pcix_reg_write4()
269 s->pim[2].la &= 0xffffffffULL; in ppc440_pcix_reg_write4()
270 s->pim[2].la |= val << 32; in ppc440_pcix_reg_write4()
275 s->sts = val; in ppc440_pcix_reg_write4()
279 s->pim[0].sa &= 0xffffffffULL; in ppc440_pcix_reg_write4()
280 s->pim[0].sa |= val << 32; in ppc440_pcix_reg_write4()
284 s->pim[2].sa &= 0xffffffffULL; in ppc440_pcix_reg_write4()
285 s->pim[2].sa |= val << 32; in ppc440_pcix_reg_write4()
305 val = ldl_le_p(s->config + addr); in ppc440_pcix_reg_read4()
309 val = s->pom[0].la; in ppc440_pcix_reg_read4()
312 val = s->pom[0].la >> 32; in ppc440_pcix_reg_read4()
315 val = s->pom[0].sa; in ppc440_pcix_reg_read4()
318 val = s->pom[0].pcia; in ppc440_pcix_reg_read4()
321 val = s->pom[0].pcia >> 32; in ppc440_pcix_reg_read4()
324 val = s->pom[1].la; in ppc440_pcix_reg_read4()
327 val = s->pom[1].la >> 32; in ppc440_pcix_reg_read4()
330 val = s->pom[1].sa; in ppc440_pcix_reg_read4()
333 val = s->pom[1].pcia; in ppc440_pcix_reg_read4()
336 val = s->pom[1].pcia >> 32; in ppc440_pcix_reg_read4()
339 val = s->pom[2].sa; in ppc440_pcix_reg_read4()
343 val = s->pim[0].sa; in ppc440_pcix_reg_read4()
346 val = s->pim[0].la; in ppc440_pcix_reg_read4()
349 val = s->pim[0].la >> 32; in ppc440_pcix_reg_read4()
352 val = s->pim[1].sa; in ppc440_pcix_reg_read4()
355 val = s->pim[1].la; in ppc440_pcix_reg_read4()
358 val = s->pim[1].la >> 32; in ppc440_pcix_reg_read4()
361 val = s->pim[2].sa; in ppc440_pcix_reg_read4()
364 val = s->pim[2].la; in ppc440_pcix_reg_read4()
367 val = s->pim[2].la >> 32; in ppc440_pcix_reg_read4()
371 val = s->sts; in ppc440_pcix_reg_read4()
375 val = s->pim[0].sa >> 32; in ppc440_pcix_reg_read4()
378 val = s->pim[2].sa >> 32; in ppc440_pcix_reg_read4()
404 ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr); in ppc440_pcix_reset()
407 ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr); in ppc440_pcix_reset()
409 memset(s->pom, 0, sizeof(s->pom)); in ppc440_pcix_reset()
410 memset(s->pim, 0, sizeof(s->pim)); in ppc440_pcix_reset()
412 s->pim[i].sa = 0xffffffff00000000ULL; in ppc440_pcix_reset()
414 s->sts = 0; in ppc440_pcix_reset()
428 trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0); in ppc440_pcix_map_irq()
448 return &s->bm_as; in ppc440_pcix_set_iommu()
457 * missing enable bit and low bits set and still expect this to work
469 s->config_reg = (val & 0xfffffffcULL) | (1UL << 31); in pci_host_config_write()
476 uint32_t val = s->config_reg; in pci_host_config_read()
496 sysbus_init_irq(sbd, &s->irq); in ppc440_pcix_realize()
497 memory_region_init(&s->busmem, OBJECT(dev), "pci-mem", UINT64_MAX); in ppc440_pcix_realize()
498 memory_region_init(&s->iomem, OBJECT(dev), "pci-io", 64 * KiB); in ppc440_pcix_realize()
499 h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq, in ppc440_pcix_realize()
500 ppc440_pcix_map_irq, &s->irq, &s->busmem, &s->iomem, in ppc440_pcix_realize()
503 memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX); in ppc440_pcix_realize()
504 memory_region_add_subregion(&s->bm, 0x0, &s->busmem); in ppc440_pcix_realize()
505 address_space_init(&s->bm_as, &s->bm, "pci-bm"); in ppc440_pcix_realize()
506 pci_setup_iommu(h->bus, &ppc440_iommu_ops, s); in ppc440_pcix_realize()
508 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE); in ppc440_pcix_realize()
509 memory_region_init_io(&h->conf_mem, OBJECT(s), &ppc440_pcix_host_conf_ops, in ppc440_pcix_realize()
510 h, "pci-conf-idx", 4); in ppc440_pcix_realize()
511 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, in ppc440_pcix_realize()
512 h, "pci-conf-data", 4); in ppc440_pcix_realize()
513 memory_region_init_io(&s->regs, OBJECT(s), &pci_reg_ops, s, "pci-reg", in ppc440_pcix_realize()
515 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); in ppc440_pcix_realize()
516 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); in ppc440_pcix_realize()
517 memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->regs); in ppc440_pcix_realize()
518 sysbus_init_mmio(sbd, &s->container); in ppc440_pcix_realize()
519 sysbus_init_mmio(sbd, &s->iomem); in ppc440_pcix_realize()
526 dc->realize = ppc440_pcix_realize; in ppc440_pcix_class_init()