90     root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;  in designware_pcie_root_msi_write()
92     if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {  in designware_pcie_root_msi_write()
110     MemoryRegion *mem   = &root->msi.iomem;  in designware_pcie_root_update_msi_mapping()
111     const uint64_t base = root->msi.base;  in designware_pcie_root_update_msi_mapping()
112     const bool enable   = root->msi.intr[0].enable;  in designware_pcie_root_update_msi_mapping()
156         val = root->msi.base;  in designware_pcie_root_config_read()
160         val = root->msi.base >> 32;  in designware_pcie_root_config_read()
164         val = root->msi.intr[0].enable;  in designware_pcie_root_config_read()
168         val = root->msi.intr[0].mask;  in designware_pcie_root_config_read()
172         val = root->msi.intr[0].status;  in designware_pcie_root_config_read()
315         root->msi.base &= 0xFFFFFFFF00000000ULL;  in designware_pcie_root_config_write()
316         root->msi.base |= val;  in designware_pcie_root_config_write()
321         root->msi.base &= 0x00000000FFFFFFFFULL;  in designware_pcie_root_config_write()
322         root->msi.base |= (uint64_t)val << 32;  in designware_pcie_root_config_write()
327         root->msi.intr[0].enable = val;  in designware_pcie_root_config_write()
332         root->msi.intr[0].mask = val;  in designware_pcie_root_config_write()
336         root->msi.intr[0].status ^= val;  in designware_pcie_root_config_write()
337         if (!root->msi.intr[0].status) {  in designware_pcie_root_config_write()
505     memory_region_init_io(&root->msi.iomem, OBJECT(root),  in designware_pcie_root_realize()
514     memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);  in designware_pcie_root_realize()
515     memory_region_set_enabled(&root->msi.iomem, false);  in designware_pcie_root_realize()
586         VMSTATE_STRUCT(msi,