Lines Matching +full:- +full:- +full:root
29 #include "hw/qdev-properties.h"
32 #include "hw/pci-host/designware.h"
61 designware_pcie_root_to_host(DesignwarePCIERoot *root) in designware_pcie_root_to_host() argument
63 BusState *bus = qdev_get_parent_bus(DEVICE(root)); in designware_pcie_root_to_host()
64 return DESIGNWARE_PCIE_HOST(bus->parent); in designware_pcie_root_to_host()
75 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
77 * well-behaved guests won't ever ask a PCI device to DMA from in designware_pcie_root_msi_read()
87 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); in designware_pcie_root_msi_write() local
88 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_msi_write()
90 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
92 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
93 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); in designware_pcie_root_msi_write()
107 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) in designware_pcie_root_update_msi_mapping() argument
110 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping()
111 const uint64_t base = root->msi.base; in designware_pcie_root_update_msi_mapping()
112 const bool enable = root->msi.intr[0].enable; in designware_pcie_root_update_msi_mapping()
119 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root) in designware_pcie_root_get_current_viewport() argument
121 const unsigned int idx = root->atu_viewport & 0xF; in designware_pcie_root_get_current_viewport()
123 !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); in designware_pcie_root_get_current_viewport()
124 return &root->viewports[dir][idx]; in designware_pcie_root_get_current_viewport()
130 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); in designware_pcie_root_config_read() local
132 designware_pcie_root_get_current_viewport(root); in designware_pcie_root_config_read()
156 val = root->msi.base; in designware_pcie_root_config_read()
160 val = root->msi.base >> 32; in designware_pcie_root_config_read()
164 val = root->msi.intr[0].enable; in designware_pcie_root_config_read()
168 val = root->msi.intr[0].mask; in designware_pcie_root_config_read()
172 val = root->msi.intr[0].status; in designware_pcie_root_config_read()
180 val = root->atu_viewport; in designware_pcie_root_config_read()
184 val = viewport->base; in designware_pcie_root_config_read()
188 val = viewport->base >> 32; in designware_pcie_root_config_read()
192 val = viewport->target; in designware_pcie_root_config_read()
196 val = viewport->target >> 32; in designware_pcie_root_config_read()
200 val = viewport->limit; in designware_pcie_root_config_read()
205 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / in designware_pcie_root_config_read()
221 DesignwarePCIERoot *root = viewport->root; in designware_pcie_root_data_access() local
223 const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); in designware_pcie_root_data_access()
224 const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); in designware_pcie_root_data_access()
225 PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); in designware_pcie_root_data_access()
229 addr &= pci_config_size(pcidev) - 1; in designware_pcie_root_data_access()
267 static void designware_pcie_update_viewport(DesignwarePCIERoot *root, in designware_pcie_update_viewport() argument
270 const uint64_t target = viewport->target; in designware_pcie_update_viewport()
271 const uint64_t base = viewport->base; in designware_pcie_update_viewport()
272 const uint64_t size = (uint64_t)viewport->limit - base + 1; in designware_pcie_update_viewport()
273 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_update_viewport()
277 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) { in designware_pcie_update_viewport()
278 current = &viewport->mem; in designware_pcie_update_viewport()
279 other = &viewport->cfg; in designware_pcie_update_viewport()
282 current = &viewport->cfg; in designware_pcie_update_viewport()
283 other = &viewport->mem; in designware_pcie_update_viewport()
302 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); in designware_pcie_root_config_write() local
303 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_config_write()
305 designware_pcie_root_get_current_viewport(root); in designware_pcie_root_config_write()
311 /* No-op */ in designware_pcie_root_config_write()
315 root->msi.base &= 0xFFFFFFFF00000000ULL; in designware_pcie_root_config_write()
316 root->msi.base |= val; in designware_pcie_root_config_write()
317 designware_pcie_root_update_msi_mapping(root); in designware_pcie_root_config_write()
321 root->msi.base &= 0x00000000FFFFFFFFULL; in designware_pcie_root_config_write()
322 root->msi.base |= (uint64_t)val << 32; in designware_pcie_root_config_write()
323 designware_pcie_root_update_msi_mapping(root); in designware_pcie_root_config_write()
327 root->msi.intr[0].enable = val; in designware_pcie_root_config_write()
328 designware_pcie_root_update_msi_mapping(root); in designware_pcie_root_config_write()
332 root->msi.intr[0].mask = val; in designware_pcie_root_config_write()
336 root->msi.intr[0].status ^= val; in designware_pcie_root_config_write()
337 if (!root->msi.intr[0].status) { in designware_pcie_root_config_write()
338 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); in designware_pcie_root_config_write()
344 (DESIGNWARE_PCIE_NUM_VIEWPORTS - 1); in designware_pcie_root_config_write()
345 root->atu_viewport = val; in designware_pcie_root_config_write()
349 viewport->base &= 0xFFFFFFFF00000000ULL; in designware_pcie_root_config_write()
350 viewport->base |= val; in designware_pcie_root_config_write()
354 viewport->base &= 0x00000000FFFFFFFFULL; in designware_pcie_root_config_write()
355 viewport->base |= (uint64_t)val << 32; in designware_pcie_root_config_write()
359 viewport->target &= 0xFFFFFFFF00000000ULL; in designware_pcie_root_config_write()
360 viewport->target |= val; in designware_pcie_root_config_write()
364 viewport->target &= 0x00000000FFFFFFFFULL; in designware_pcie_root_config_write()
365 viewport->target |= val; in designware_pcie_root_config_write()
369 viewport->limit = val; in designware_pcie_root_config_write()
373 viewport->cr[0] = val; in designware_pcie_root_config_write()
376 viewport->cr[1] = val; in designware_pcie_root_config_write()
377 designware_pcie_update_viewport(root, viewport); in designware_pcie_root_config_write()
396 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); in designware_pcie_root_realize() local
397 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_realize()
399 MemoryRegion *address_space = &host->pci.memory; in designware_pcie_root_realize()
410 br->bus_name = "dw-pcie"; in designware_pcie_root_realize()
412 pci_set_word(dev->config + PCI_COMMAND, in designware_pcie_root_realize()
415 pci_config_set_interrupt_pin(dev->config, 1); in designware_pcie_root_realize()
431 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; in designware_pcie_root_realize()
432 viewport->inbound = true; in designware_pcie_root_realize()
433 viewport->base = 0x0000000000000000ULL; in designware_pcie_root_realize()
434 viewport->target = 0x0000000000000000ULL; in designware_pcie_root_realize()
435 viewport->limit = UINT32_MAX; in designware_pcie_root_realize()
436 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
438 source = &host->pci.address_space_root; in designware_pcie_root_realize()
443 * Configure MemoryRegion implementing PCI -> CPU memory in designware_pcie_root_realize()
446 mem = &viewport->mem; in designware_pcie_root_realize()
448 memory_region_init_alias(mem, OBJECT(root), name, destination, in designware_pcie_root_realize()
450 memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); in designware_pcie_root_realize()
454 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; in designware_pcie_root_realize()
455 viewport->root = root; in designware_pcie_root_realize()
456 viewport->inbound = false; in designware_pcie_root_realize()
457 viewport->base = 0x0000000000000000ULL; in designware_pcie_root_realize()
458 viewport->target = 0x0000000000000000ULL; in designware_pcie_root_realize()
459 viewport->limit = UINT32_MAX; in designware_pcie_root_realize()
460 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
462 destination = &host->pci.memory; in designware_pcie_root_realize()
467 * Configure MemoryRegion implementing CPU -> PCI memory in designware_pcie_root_realize()
470 mem = &viewport->mem; in designware_pcie_root_realize()
472 memory_region_init_alias(mem, OBJECT(root), name, destination, in designware_pcie_root_realize()
482 mem = &viewport->cfg; in designware_pcie_root_realize()
484 memory_region_init_io(&viewport->cfg, OBJECT(root), in designware_pcie_root_realize()
501 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; in designware_pcie_root_realize()
502 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_root_realize()
503 designware_pcie_update_viewport(root, viewport); in designware_pcie_root_realize()
505 memory_region_init_io(&root->msi.iomem, OBJECT(root), in designware_pcie_root_realize()
507 root, "pcie-msi", 0x4); in designware_pcie_root_realize()
514 memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem); in designware_pcie_root_realize()
515 memory_region_set_enabled(&root->msi.iomem, false); in designware_pcie_root_realize()
522 qemu_set_irq(host->pci.irqs[irq_num], level); in designware_pcie_set_irq()
532 .name = "designware-pcie-msi-bank",
544 .name = "designware-pcie-msi",
560 .name = "designware-pcie-viewport",
573 .name = "designware-pcie-root",
600 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in designware_pcie_root_class_init()
602 k->vendor_id = PCI_VENDOR_ID_SYNOPSYS; in designware_pcie_root_class_init()
603 k->device_id = 0xABCD; in designware_pcie_root_class_init()
604 k->revision = 0; in designware_pcie_root_class_init()
605 k->class_id = PCI_CLASS_BRIDGE_PCI; in designware_pcie_root_class_init()
606 k->exit = pci_bridge_exitfn; in designware_pcie_root_class_init()
607 k->realize = designware_pcie_root_realize; in designware_pcie_root_class_init()
608 k->config_read = designware_pcie_root_config_read; in designware_pcie_root_class_init()
609 k->config_write = designware_pcie_root_config_write; in designware_pcie_root_class_init()
613 * PCI-facing part of the host bridge, not usable without the in designware_pcie_root_class_init()
614 * host-facing part, which can't be device_add'ed, yet. in designware_pcie_root_class_init()
616 dc->user_creatable = false; in designware_pcie_root_class_init()
617 dc->vmsd = &vmstate_designware_pcie_root; in designware_pcie_root_class_init()
624 PCIDevice *device = pci_find_device(pci->bus, 0, 0); in designware_pcie_host_mmio_read()
636 PCIDevice *device = pci_find_device(pci->bus, 0, 0); in designware_pcie_host_mmio_write()
666 return &s->pci.address_space; in designware_pcie_host_set_iommu()
680 for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { in designware_pcie_host_realize()
681 sysbus_init_irq(sbd, &s->pci.irqs[i]); in designware_pcie_host_realize()
684 memory_region_init_io(&s->mmio, in designware_pcie_host_realize()
689 sysbus_init_mmio(sbd, &s->mmio); in designware_pcie_host_realize()
691 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); in designware_pcie_host_realize()
692 memory_region_init(&s->pci.memory, OBJECT(s), in designware_pcie_host_realize()
693 "pcie-bus-memory", in designware_pcie_host_realize()
696 pci->bus = pci_register_root_bus(dev, "pcie", in designware_pcie_host_realize()
700 &s->pci.memory, in designware_pcie_host_realize()
701 &s->pci.io, in designware_pcie_host_realize()
704 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in designware_pcie_host_realize()
706 memory_region_init(&s->pci.address_space_root, in designware_pcie_host_realize()
708 "pcie-bus-address-space-root", in designware_pcie_host_realize()
710 memory_region_add_subregion(&s->pci.address_space_root, in designware_pcie_host_realize()
711 0x0, &s->pci.memory); in designware_pcie_host_realize()
712 address_space_init(&s->pci.address_space, in designware_pcie_host_realize()
713 &s->pci.address_space_root, in designware_pcie_host_realize()
714 "pcie-bus-address-space"); in designware_pcie_host_realize()
715 pci_setup_iommu(pci->bus, &designware_iommu_ops, s); in designware_pcie_host_realize()
717 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); in designware_pcie_host_realize()
721 .name = "designware-pcie-host",
725 VMSTATE_STRUCT(root,
739 hc->root_bus_path = designware_pcie_host_root_bus_path; in designware_pcie_host_class_init()
740 dc->realize = designware_pcie_host_realize; in designware_pcie_host_class_init()
741 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in designware_pcie_host_class_init()
742 dc->fw_name = "pci"; in designware_pcie_host_class_init()
743 dc->vmsd = &vmstate_designware_pcie_host; in designware_pcie_host_class_init()
749 DesignwarePCIERoot *root = &s->root; in designware_pcie_host_init() local
751 object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT); in designware_pcie_host_init()
752 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); in designware_pcie_host_init()
753 qdev_prop_set_bit(DEVICE(root), "multifunction", false); in designware_pcie_host_init()