Lines Matching +full:43 +full:s
191 #define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
192 #define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
193 #define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
194 #define EFUSE_AES_WR_LK BIT_POS(43, 11)
195 #define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
196 #define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
197 #define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
198 #define EFUSE_DNA_WR_LK BIT_POS(43, 27)
199 #define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
208 #define EFUSE_KEY_CRC_LK_ROW (43)
227 static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s) in efuse_imr_update_irq() argument
229 bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR]; in efuse_imr_update_irq()
230 qemu_set_irq(s->irq_efuse_imr, pending); in efuse_imr_update_irq()
235 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_isr_postw() local
236 efuse_imr_update_irq(s); in efuse_isr_postw()
241 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_ier_prew() local
244 s->regs[R_EFUSE_IMR] &= ~val; in efuse_ier_prew()
245 efuse_imr_update_irq(s); in efuse_ier_prew()
251 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_idr_prew() local
254 s->regs[R_EFUSE_IMR] |= val; in efuse_idr_prew()
255 efuse_imr_update_irq(s); in efuse_idr_prew()
259 static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s) in efuse_status_tbits_sync() argument
261 uint32_t check = xlnx_efuse_tbits_check(s->efuse); in efuse_status_tbits_sync()
262 uint32_t val = s->regs[R_STATUS]; in efuse_status_tbits_sync()
268 s->regs[R_STATUS] = val; in efuse_status_tbits_sync()
271 static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s) in efuse_anchor_bits_check() argument
275 if (!s->efuse || !s->efuse->init_tbits) { in efuse_anchor_bits_check()
279 for (page = 0; page < s->efuse->efuse_nr; page++) { in efuse_anchor_bits_check()
286 if (!xlnx_efuse_get_bit(s->efuse, bit)) { in efuse_anchor_bits_check()
287 xlnx_efuse_set_bit(s->efuse, bit); in efuse_anchor_bits_check()
291 if (!xlnx_efuse_get_bit(s->efuse, bit)) { in efuse_anchor_bits_check()
292 xlnx_efuse_set_bit(s->efuse, bit); in efuse_anchor_bits_check()
301 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_key_crc_check() local
308 r = s->regs[R_STATUS] | done_mask | pass_mask; in efuse_key_crc_check()
310 lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask; in efuse_key_crc_check()
311 if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) { in efuse_key_crc_check()
315 s->regs[R_STATUS] = r ^ pass_mask; in efuse_key_crc_check()
318 static void efuse_data_sync(XlnxVersalEFuseCtrl *s) in efuse_data_sync() argument
320 efuse_status_tbits_sync(s); in efuse_data_sync()
331 static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s) in efuse_lk_spec_sort() argument
333 XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; in efuse_lk_spec_sort()
334 const uint32_t n8 = s->extra_pg0_lock_n16 * 2; in efuse_lk_spec_sort()
343 static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row) in efuse_lk_spec_find() argument
345 const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; in efuse_lk_spec_find()
346 const uint32_t n8 = s->extra_pg0_lock_n16 * 2; in efuse_lk_spec_find()
360 static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit) in efuse_bit_locked() argument
379 return lk_bit ? lk_bit : efuse_lk_spec_find(s, row); in efuse_bit_locked()
382 static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit) in efuse_pgm_locked() argument
388 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in efuse_pgm_locked()
395 if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) && in efuse_pgm_locked()
400 lock = efuse_bit_locked(s, bit); in efuse_pgm_locked()
417 lock = xlnx_efuse_get_bit(s->efuse, lock); in efuse_pgm_locked()
426 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_pgm_addr_postw() local
431 s->regs[R_EFUSE_PGM_ADDR] = 0; in efuse_pgm_addr_postw()
442 if (efuse_pgm_locked(s, bit)) { in efuse_pgm_addr_postw()
443 g_autofree char *path = object_get_canonical_path(OBJECT(s)); in efuse_pgm_addr_postw()
446 "%s: Denied setting of efuse<%u, %u, %u>\n", in efuse_pgm_addr_postw()
451 } else if (xlnx_efuse_set_bit(s->efuse, bit)) { in efuse_pgm_addr_postw()
454 efuse_status_tbits_sync(s); in efuse_pgm_addr_postw()
459 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in efuse_pgm_addr_postw()
462 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in efuse_pgm_addr_postw()
463 efuse_imr_update_irq(s); in efuse_pgm_addr_postw()
468 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_rd_addr_postw() local
473 s->regs[R_EFUSE_RD_ADDR] = 0; in efuse_rd_addr_postw()
481 s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse, in efuse_rd_addr_postw()
484 g_autofree char *path = object_get_canonical_path(OBJECT(s)); in efuse_rd_addr_postw()
487 "%s: Denied reading of efuse<%u, %u>\n", in efuse_rd_addr_postw()
492 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in efuse_rd_addr_postw()
495 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in efuse_rd_addr_postw()
496 efuse_imr_update_irq(s); in efuse_rd_addr_postw()
502 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_cache_load_prew() local
505 efuse_data_sync(s); in efuse_cache_load_prew()
507 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in efuse_cache_load_prew()
508 efuse_imr_update_irq(s); in efuse_cache_load_prew()
516 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); in efuse_pgm_lock_prew() local
522 val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK); in efuse_pgm_lock_prew()
622 XlnxVersalEFuseCtrl *s; in efuse_ctrl_reg_write() local
630 s = XLNX_VERSAL_EFUSE_CTRL(dev); in efuse_ctrl_reg_write()
632 if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { in efuse_ctrl_reg_write()
633 g_autofree char *path = object_get_canonical_path(OBJECT(s)); in efuse_ctrl_reg_write()
636 "%s[reg_0x%02lx]: Attempt to write locked register.\n", in efuse_ctrl_reg_write()
663 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); in efuse_ctrl_reset_hold() local
666 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in efuse_ctrl_reset_hold()
667 efuse_ctrl_register_reset(&s->regs_info[i]); in efuse_ctrl_reset_hold()
670 efuse_anchor_bits_check(s); in efuse_ctrl_reset_hold()
671 efuse_data_sync(s); in efuse_ctrl_reset_hold()
672 efuse_imr_update_irq(s); in efuse_ctrl_reset_hold()
687 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); in efuse_ctrl_realize() local
690 if (!s->efuse) { in efuse_ctrl_realize()
691 g_autofree char *path = object_get_canonical_path(OBJECT(s)); in efuse_ctrl_realize()
693 error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", in efuse_ctrl_realize()
699 if ((s->extra_pg0_lock_n16 % lks_sz) != 0) { in efuse_ctrl_realize()
700 g_autofree char *path = object_get_canonical_path(OBJECT(s)); in efuse_ctrl_realize()
703 "%s.pg0-lock: array property item-count not multiple of %u", in efuse_ctrl_realize()
708 efuse_lk_spec_sort(s); in efuse_ctrl_realize()
713 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); in efuse_ctrl_init() local
716 s->reg_array = in efuse_ctrl_init()
719 s->regs_info, s->regs, in efuse_ctrl_init()
724 sysbus_init_mmio(sbd, &s->reg_array->mem); in efuse_ctrl_init()
725 sysbus_init_irq(sbd, &s->irq_efuse_imr); in efuse_ctrl_init()
730 XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); in efuse_ctrl_finalize() local
732 register_finalize_block(s->reg_array); in efuse_ctrl_finalize()
733 g_free(s->extra_pg0_lock_spec); in efuse_ctrl_finalize()