Lines Matching +full:tx +full:- +full:ping +full:- +full:pong
7 * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite
36 #include "hw/qdev-properties.h"
37 #include "hw/qdev-properties-system.h"
82 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
107 if (s->port[0].reg.tx_gie & GIE_GIE) { in eth_pulse_irq()
108 qemu_irq_pulse(s->irq); in eth_pulse_irq()
119 return memory_region_get_ram_ptr(&s->port[port_index].txbuf); in txbuf_ptr()
124 return memory_region_get_ram_ptr(&s->port[port_index].rxbuf); in rxbuf_ptr()
135 r = s->port[port_index].reg.tx_len; in port_tx_read()
138 r = s->port[port_index].reg.tx_gie; in port_tx_read()
141 r = s->port[port_index].reg.tx_ctrl; in port_tx_read()
158 s->port[port_index].reg.tx_len = value; in port_tx_write()
161 s->port[port_index].reg.tx_gie = value; in port_tx_write()
165 qemu_send_packet(qemu_get_queue(s->nic), in port_tx_write()
167 s->port[port_index].reg.tx_len); in port_tx_write()
168 if (s->port[port_index].reg.tx_ctrl & CTRL_I) { in port_tx_write()
172 memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); in port_tx_write()
173 if (s->port[port_index].reg.tx_ctrl & CTRL_I) { in port_tx_write()
181 s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); in port_tx_write()
213 r = s->port[port_index].reg.rx_ctrl; in port_rx_read()
231 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in port_rx_write()
233 s->port[port_index].reg.rx_ctrl = value; in port_rx_write()
261 return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S); in eth_can_rx()
267 unsigned int port_index = s->port_index; in eth_rx()
270 if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) in eth_rx()
273 if (s->port[port_index].reg.rx_ctrl & CTRL_S) { in eth_rx()
274 trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl); in eth_rx()
275 return -1; in eth_rx()
280 return -1; in eth_rx()
284 s->port[port_index].reg.rx_ctrl |= CTRL_S; in eth_rx()
285 if (s->port[port_index].reg.rx_ctrl & CTRL_I) { in eth_rx()
290 s->port_index ^= s->c_rx_pingpong; in eth_rx()
298 s->port_index = 0; in xilinx_ethlite_reset()
313 if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) { in xilinx_ethlite_realize()
318 ops_index = s->model_endianness == ENDIAN_MODE_BIG ? 1 : 0; in xilinx_ethlite_realize()
320 memory_region_init(&s->container, OBJECT(dev), in xilinx_ethlite_realize()
321 "xlnx.xps-ethernetlite", 0x2000); in xilinx_ethlite_realize()
323 object_initialize_child(OBJECT(dev), "ethlite.reserved", &s->rsvd, in xilinx_ethlite_realize()
325 qdev_prop_set_string(DEVICE(&s->rsvd), "name", "ethlite.reserved"); in xilinx_ethlite_realize()
326 qdev_prop_set_uint64(DEVICE(&s->rsvd), "size", in xilinx_ethlite_realize()
327 memory_region_size(&s->container)); in xilinx_ethlite_realize()
328 sysbus_realize(SYS_BUS_DEVICE(&s->rsvd), &error_fatal); in xilinx_ethlite_realize()
329 memory_region_add_subregion_overlap(&s->container, 0, in xilinx_ethlite_realize()
330 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rsvd), 0), in xilinx_ethlite_realize()
331 -1); in xilinx_ethlite_realize()
333 object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, in xilinx_ethlite_realize()
335 qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio"); in xilinx_ethlite_realize()
336 qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4); in xilinx_ethlite_realize()
337 sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal); in xilinx_ethlite_realize()
338 memory_region_add_subregion(&s->container, A_MDIO_BASE, in xilinx_ethlite_realize()
339 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); in xilinx_ethlite_realize()
342 memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev), in xilinx_ethlite_realize()
343 i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf", in xilinx_ethlite_realize()
345 memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf); in xilinx_ethlite_realize()
346 memory_region_init_io(&s->port[i].txio, OBJECT(dev), in xilinx_ethlite_realize()
348 i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", in xilinx_ethlite_realize()
350 memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0, in xilinx_ethlite_realize()
351 &s->port[i].txio); in xilinx_ethlite_realize()
353 memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev), in xilinx_ethlite_realize()
356 memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i, in xilinx_ethlite_realize()
357 &s->port[i].rxbuf); in xilinx_ethlite_realize()
358 memory_region_init_io(&s->port[i].rxio, OBJECT(dev), in xilinx_ethlite_realize()
362 memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0, in xilinx_ethlite_realize()
363 &s->port[i].rxio); in xilinx_ethlite_realize()
366 qemu_macaddr_default_if_unset(&s->conf.macaddr); in xilinx_ethlite_realize()
367 s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, in xilinx_ethlite_realize()
368 object_get_typename(OBJECT(dev)), dev->id, in xilinx_ethlite_realize()
369 &dev->mem_reentrancy_guard, s); in xilinx_ethlite_realize()
370 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in xilinx_ethlite_realize()
377 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); in xilinx_ethlite_init()
378 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); in xilinx_ethlite_init()
383 DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
384 DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
392 dc->realize = xilinx_ethlite_realize; in xilinx_ethlite_class_init()