Lines Matching +full:build +full:- +full:tci
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
55 #include "hw/qdev-properties.h"
75 ( ( input ) & ( size - 1 ) )
111 Timer = 0x48, /* A general-purpose counter. */
119 Config4 = 0x5A, /* absent on RTL-8139A */
134 Config5 = 0xD8, /* absent on RTL-8139A */
140 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
141 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
224 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
225 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
324 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
372 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
500 /* Non-persistent data */
528 eeprom->address = command & EEPROM_9346_ADDR_MASK; in prom9346_decode_command()
529 eeprom->output = eeprom->contents[eeprom->address]; in prom9346_decode_command()
530 eeprom->eedo = 0; in prom9346_decode_command()
531 eeprom->tick = 0; in prom9346_decode_command()
532 eeprom->mode = Chip9346_data_read; in prom9346_decode_command()
534 eeprom->address, eeprom->output); in prom9346_decode_command()
540 eeprom->address = command & EEPROM_9346_ADDR_MASK; in prom9346_decode_command()
541 eeprom->input = 0; in prom9346_decode_command()
542 eeprom->tick = 0; in prom9346_decode_command()
543 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ in prom9346_decode_command()
545 eeprom->address); in prom9346_decode_command()
549 eeprom->mode = Chip9346_none; in prom9346_decode_command()
568 int bit = eeprom->eedi?1:0; in prom9346_shift_clock()
570 ++ eeprom->tick; in prom9346_shift_clock()
572 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, in prom9346_shift_clock()
573 eeprom->eedo); in prom9346_shift_clock()
575 switch (eeprom->mode) in prom9346_shift_clock()
580 eeprom->mode = Chip9346_read_command; in prom9346_shift_clock()
581 eeprom->tick = 0; in prom9346_shift_clock()
582 eeprom->input = 0; in prom9346_shift_clock()
588 eeprom->input = (eeprom->input << 1) | (bit & 1); in prom9346_shift_clock()
589 if (eeprom->tick == 8) in prom9346_shift_clock()
591 prom9346_decode_command(eeprom, eeprom->input & 0xff); in prom9346_shift_clock()
596 eeprom->eedo = (eeprom->output & 0x8000)?1:0; in prom9346_shift_clock()
597 eeprom->output <<= 1; in prom9346_shift_clock()
598 if (eeprom->tick == 16) in prom9346_shift_clock()
603 // so we need to enter wait-for-command state here in prom9346_shift_clock()
604 eeprom->mode = Chip9346_enter_command_mode; in prom9346_shift_clock()
605 eeprom->input = 0; in prom9346_shift_clock()
606 eeprom->tick = 0; in prom9346_shift_clock()
611 ++eeprom->address; in prom9346_shift_clock()
612 eeprom->address &= EEPROM_9346_ADDR_MASK; in prom9346_shift_clock()
613 eeprom->output = eeprom->contents[eeprom->address]; in prom9346_shift_clock()
614 eeprom->tick = 0; in prom9346_shift_clock()
617 eeprom->address, eeprom->output); in prom9346_shift_clock()
623 eeprom->input = (eeprom->input << 1) | (bit & 1); in prom9346_shift_clock()
624 if (eeprom->tick == 16) in prom9346_shift_clock()
627 eeprom->address, eeprom->input); in prom9346_shift_clock()
629 eeprom->contents[eeprom->address] = eeprom->input; in prom9346_shift_clock()
630 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ in prom9346_shift_clock()
631 eeprom->tick = 0; in prom9346_shift_clock()
632 eeprom->input = 0; in prom9346_shift_clock()
637 eeprom->input = (eeprom->input << 1) | (bit & 1); in prom9346_shift_clock()
638 if (eeprom->tick == 16) in prom9346_shift_clock()
643 eeprom->contents[i] = eeprom->input; in prom9346_shift_clock()
645 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); in prom9346_shift_clock()
647 eeprom->mode = Chip9346_enter_command_mode; in prom9346_shift_clock()
648 eeprom->tick = 0; in prom9346_shift_clock()
649 eeprom->input = 0; in prom9346_shift_clock()
660 EEprom9346 *eeprom = &s->eeprom; in prom9346_get_wire()
661 if (!eeprom->eecs) in prom9346_get_wire()
664 return eeprom->eedo; in prom9346_get_wire()
670 EEprom9346 *eeprom = &s->eeprom; in prom9346_set_wire()
671 uint8_t old_eecs = eeprom->eecs; in prom9346_set_wire()
672 uint8_t old_eesk = eeprom->eesk; in prom9346_set_wire()
674 eeprom->eecs = eecs; in prom9346_set_wire()
675 eeprom->eesk = eesk; in prom9346_set_wire()
676 eeprom->eedi = eedi; in prom9346_set_wire()
678 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, in prom9346_set_wire()
679 eeprom->eesk, eeprom->eedi, eeprom->eedo); in prom9346_set_wire()
684 eeprom->tick = 0; in prom9346_set_wire()
685 eeprom->input = 0; in prom9346_set_wire()
686 eeprom->output = 0; in prom9346_set_wire()
687 eeprom->mode = Chip9346_enter_command_mode; in prom9346_set_wire()
709 isr = (s->IntrStatus & s->IntrMask) & 0xffff; in rtl8139_update_irq()
711 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, in rtl8139_update_irq()
712 s->IntrMask); in rtl8139_update_irq()
720 return (s->RxConfig & (1 << 7)); in rtl8139_RxWrap()
725 return s->bChipCmdState & CmdRxEnb; in rtl8139_receiver_enabled()
730 return s->bChipCmdState & CmdTxEnb; in rtl8139_transmitter_enabled()
735 return s->CpCmd & CPlusRxEnb; in rtl8139_cp_receiver_enabled()
740 return s->CpCmd & CPlusTxEnb; in rtl8139_cp_transmitter_enabled()
747 if (s->RxBufAddr + size > s->RxBufferSize) in rtl8139_write_buffer()
749 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); in rtl8139_write_buffer()
752 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) in rtl8139_write_buffer()
754 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); in rtl8139_write_buffer()
758 pci_dma_write(d, s->RxBuf + s->RxBufAddr, in rtl8139_write_buffer()
759 buf, size-wrapped); in rtl8139_write_buffer()
763 s->RxBufAddr = 0; in rtl8139_write_buffer()
765 pci_dma_write(d, s->RxBuf + s->RxBufAddr, in rtl8139_write_buffer()
766 buf + (size-wrapped), wrapped); in rtl8139_write_buffer()
768 s->RxBufAddr = wrapped; in rtl8139_write_buffer()
774 /* non-wrapping path or overwrapping enabled */ in rtl8139_write_buffer()
775 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); in rtl8139_write_buffer()
777 s->RxBufAddr += size; in rtl8139_write_buffer()
790 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); in rtl8139_cp_rx_valid()
799 if (!s->clock_enabled) { in rtl8139_can_receive()
812 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, in rtl8139_can_receive()
813 s->RxBufferSize); in rtl8139_can_receive()
814 return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow); in rtl8139_can_receive()
833 if (!s->clock_enabled) in rtl8139_do_receive()
836 return -1; in rtl8139_do_receive()
844 return -1; in rtl8139_do_receive()
848 if (s->RxConfig & AcceptAllPhys) { in rtl8139_do_receive()
855 if (!(s->RxConfig & AcceptBroadcast)) in rtl8139_do_receive()
860 ++s->tally_counters.RxERR; in rtl8139_do_receive()
870 ++s->tally_counters.RxOkBrd; in rtl8139_do_receive()
874 if (!(s->RxConfig & AcceptMulticast)) in rtl8139_do_receive()
879 ++s->tally_counters.RxERR; in rtl8139_do_receive()
886 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) in rtl8139_do_receive()
891 ++s->tally_counters.RxERR; in rtl8139_do_receive()
901 ++s->tally_counters.RxOkMul; in rtl8139_do_receive()
903 } else if (s->phys[0] == buf[0] && in rtl8139_do_receive()
904 s->phys[1] == buf[1] && in rtl8139_do_receive()
905 s->phys[2] == buf[2] && in rtl8139_do_receive()
906 s->phys[3] == buf[3] && in rtl8139_do_receive()
907 s->phys[4] == buf[4] && in rtl8139_do_receive()
908 s->phys[5] == buf[5]) { in rtl8139_do_receive()
910 if (!(s->RxConfig & AcceptMyPhys)) in rtl8139_do_receive()
915 ++s->tally_counters.RxERR; in rtl8139_do_receive()
925 ++s->tally_counters.RxOkPhy; in rtl8139_do_receive()
932 ++s->tally_counters.RxERR; in rtl8139_do_receive()
953 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) in rtl8139_do_receive()
957 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) in rtl8139_do_receive()
961 int descriptor = s->currCPlusRxDesc; in rtl8139_do_receive()
964 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); in rtl8139_do_receive()
968 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, in rtl8139_do_receive()
969 s->RxRingAddrLO, cplus_rx_ring_desc); in rtl8139_do_receive()
990 s->IntrStatus |= RxOverflow; in rtl8139_do_receive()
991 ++s->RxMissed; in rtl8139_do_receive()
994 ++s->tally_counters.RxERR; in rtl8139_do_receive()
995 ++s->tally_counters.MissPkt; in rtl8139_do_receive()
1004 if (s->CpCmd & CPlusRxVLAN && in rtl8139_do_receive()
1007 size -= VLAN_HLEN; in rtl8139_do_receive()
1017 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", in rtl8139_do_receive()
1031 s->IntrStatus |= RxOverflow; in rtl8139_do_receive()
1032 ++s->RxMissed; in rtl8139_do_receive()
1035 ++s->tally_counters.RxERR; in rtl8139_do_receive()
1036 ++s->tally_counters.MissPkt; in rtl8139_do_receive()
1049 size - 2 * ETH_ALEN); in rtl8139_do_receive()
1054 if (s->CpCmd & CPlusRxChkSum) in rtl8139_do_receive()
1069 /* physical-matching packet flag */ in rtl8139_do_receive()
1112 ++s->tally_counters.RxOk; in rtl8139_do_receive()
1117 s->currCPlusRxDesc = 0; in rtl8139_do_receive()
1121 ++s->currCPlusRxDesc; in rtl8139_do_receive()
1124 DPRINTF("done C+ Rx mode ----------------\n"); in rtl8139_do_receive()
1132 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); in rtl8139_do_receive()
1142 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); in rtl8139_do_receive()
1144 s->IntrStatus |= RxOverflow; in rtl8139_do_receive()
1145 ++s->RxMissed; in rtl8139_do_receive()
1166 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); in rtl8139_do_receive()
1171 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); in rtl8139_do_receive()
1174 s->IntrStatus |= RxOK; in rtl8139_do_receive()
1191 s->RxBufferSize = bufferSize; in rtl8139_reset_rxring()
1192 s->RxBufPtr = 0; in rtl8139_reset_rxring()
1193 s->RxBufAddr = 0; in rtl8139_reset_rxring()
1198 s->BasicModeStatus = 0x7809; in rtl8139_reset_phy()
1199 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ in rtl8139_reset_phy()
1201 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; in rtl8139_reset_phy()
1203 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ in rtl8139_reset_phy()
1204 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ in rtl8139_reset_phy()
1205 s->NWayExpansion = 0x0001; /* autonegotiation supported */ in rtl8139_reset_phy()
1207 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; in rtl8139_reset_phy()
1216 memcpy(s->phys, s->conf.macaddr.a, 6); in rtl8139_reset()
1217 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); in rtl8139_reset()
1220 s->IntrStatus = 0; in rtl8139_reset()
1221 s->IntrMask = 0; in rtl8139_reset()
1228 s->TxStatus[i] = TxHostOwns; in rtl8139_reset()
1231 s->currTxDesc = 0; in rtl8139_reset()
1232 s->currCPlusRxDesc = 0; in rtl8139_reset()
1233 s->currCPlusTxDesc = 0; in rtl8139_reset()
1235 s->RxRingAddrLO = 0; in rtl8139_reset()
1236 s->RxRingAddrHI = 0; in rtl8139_reset()
1238 s->RxBuf = 0; in rtl8139_reset()
1243 s->TxConfig = 0; in rtl8139_reset()
1246 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk in rtl8139_reset()
1247 s->clock_enabled = 0; in rtl8139_reset()
1249 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake in rtl8139_reset()
1250 s->clock_enabled = 1; in rtl8139_reset()
1253 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; in rtl8139_reset()
1256 s->Config0 = 0x0; /* No boot ROM */ in rtl8139_reset()
1257 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ in rtl8139_reset()
1258 s->Config3 = 0x1; /* fast back-to-back compatible */ in rtl8139_reset()
1259 s->Config5 = 0x0; in rtl8139_reset()
1261 s->CpCmd = 0x0; /* reset C+ mode */ in rtl8139_reset()
1262 s->cplus_enabled = 0; in rtl8139_reset()
1264 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation in rtl8139_reset()
1265 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex in rtl8139_reset()
1266 s->BasicModeCtrl = 0x1000; // autonegotiation in rtl8139_reset()
1271 s->TCTR = 0; in rtl8139_reset()
1272 s->TimerInt = 0; in rtl8139_reset()
1273 s->TCTR_base = 0; in rtl8139_reset()
1277 RTL8139TallyCounters_clear(&s->tally_counters); in rtl8139_reset()
1282 counters->TxOk = 0; in RTL8139TallyCounters_clear()
1283 counters->RxOk = 0; in RTL8139TallyCounters_clear()
1284 counters->TxERR = 0; in RTL8139TallyCounters_clear()
1285 counters->RxERR = 0; in RTL8139TallyCounters_clear()
1286 counters->MissPkt = 0; in RTL8139TallyCounters_clear()
1287 counters->FAE = 0; in RTL8139TallyCounters_clear()
1288 counters->Tx1Col = 0; in RTL8139TallyCounters_clear()
1289 counters->TxMCol = 0; in RTL8139TallyCounters_clear()
1290 counters->RxOkPhy = 0; in RTL8139TallyCounters_clear()
1291 counters->RxOkBrd = 0; in RTL8139TallyCounters_clear()
1292 counters->RxOkMul = 0; in RTL8139TallyCounters_clear()
1293 counters->TxAbt = 0; in RTL8139TallyCounters_clear()
1294 counters->TxUndrn = 0; in RTL8139TallyCounters_clear()
1300 RTL8139TallyCounters *tally_counters = &s->tally_counters; in RTL8139TallyCounters_dma_write()
1305 val64 = cpu_to_le64(tally_counters->TxOk); in RTL8139TallyCounters_dma_write()
1308 val64 = cpu_to_le64(tally_counters->RxOk); in RTL8139TallyCounters_dma_write()
1311 val64 = cpu_to_le64(tally_counters->TxERR); in RTL8139TallyCounters_dma_write()
1314 val32 = cpu_to_le32(tally_counters->RxERR); in RTL8139TallyCounters_dma_write()
1317 val16 = cpu_to_le16(tally_counters->MissPkt); in RTL8139TallyCounters_dma_write()
1320 val16 = cpu_to_le16(tally_counters->FAE); in RTL8139TallyCounters_dma_write()
1323 val32 = cpu_to_le32(tally_counters->Tx1Col); in RTL8139TallyCounters_dma_write()
1326 val32 = cpu_to_le32(tally_counters->TxMCol); in RTL8139TallyCounters_dma_write()
1329 val64 = cpu_to_le64(tally_counters->RxOkPhy); in RTL8139TallyCounters_dma_write()
1332 val64 = cpu_to_le64(tally_counters->RxOkBrd); in RTL8139TallyCounters_dma_write()
1335 val32 = cpu_to_le32(tally_counters->RxOkMul); in RTL8139TallyCounters_dma_write()
1338 val16 = cpu_to_le16(tally_counters->TxAbt); in RTL8139TallyCounters_dma_write()
1341 val16 = cpu_to_le16(tally_counters->TxUndrn); in RTL8139TallyCounters_dma_write()
1362 s->currCPlusRxDesc = 0; in rtl8139_ChipCmd_write()
1368 s->currCPlusTxDesc = 0; in rtl8139_ChipCmd_write()
1372 val = SET_MASKED(val, 0xe3, s->bChipCmdState); in rtl8139_ChipCmd_write()
1377 s->bChipCmdState = val; in rtl8139_ChipCmd_write()
1382 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); in rtl8139_RxBufferEmpty()
1397 uint32_t ret = s->bChipCmdState; in rtl8139_ChipCmd_read()
1413 s->cplus_enabled = 1; in rtl8139_CpCmd_write()
1416 val = SET_MASKED(val, 0xff84, s->CpCmd); in rtl8139_CpCmd_write()
1418 s->CpCmd = val; in rtl8139_CpCmd_write()
1423 uint32_t ret = s->CpCmd; in rtl8139_CpCmd_read()
1446 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) in rtl8139_config_writable()
1451 DPRINTF("Configuration registers are write-protected\n"); in rtl8139_config_writable()
1467 /* Speed setting and autonegotiation enable bits are read-only */ in rtl8139_BasicModeCtrl_write()
1469 /* Duplex mode setting is read-only */ in rtl8139_BasicModeCtrl_write()
1478 val = SET_MASKED(val, mask, s->BasicModeCtrl); in rtl8139_BasicModeCtrl_write()
1480 s->BasicModeCtrl = val; in rtl8139_BasicModeCtrl_write()
1485 uint32_t ret = s->BasicModeCtrl; in rtl8139_BasicModeCtrl_read()
1499 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); in rtl8139_BasicModeStatus_write()
1501 s->BasicModeStatus = val; in rtl8139_BasicModeStatus_write()
1506 uint32_t ret = s->BasicModeStatus; in rtl8139_BasicModeStatus_read()
1522 val = SET_MASKED(val, 0x31, s->Cfg9346); in rtl8139_Cfg9346_write()
1539 s->Cfg9346 = val; in rtl8139_Cfg9346_write()
1544 uint32_t ret = s->Cfg9346; in rtl8139_Cfg9346_read()
1578 val = SET_MASKED(val, 0xf8, s->Config0); in rtl8139_Config0_write()
1580 s->Config0 = val; in rtl8139_Config0_write()
1585 uint32_t ret = s->Config0; in rtl8139_Config0_read()
1603 val = SET_MASKED(val, 0xC, s->Config1); in rtl8139_Config1_write()
1605 s->Config1 = val; in rtl8139_Config1_write()
1610 uint32_t ret = s->Config1; in rtl8139_Config1_read()
1628 val = SET_MASKED(val, 0x8F, s->Config3); in rtl8139_Config3_write()
1630 s->Config3 = val; in rtl8139_Config3_write()
1635 uint32_t ret = s->Config3; in rtl8139_Config3_read()
1653 val = SET_MASKED(val, 0x0a, s->Config4); in rtl8139_Config4_write()
1655 s->Config4 = val; in rtl8139_Config4_write()
1660 uint32_t ret = s->Config4; in rtl8139_Config4_read()
1674 val = SET_MASKED(val, 0x80, s->Config5); in rtl8139_Config5_write()
1676 s->Config5 = val; in rtl8139_Config5_write()
1681 uint32_t ret = s->Config5; in rtl8139_Config5_read()
1698 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); in rtl8139_TxConfig_write()
1700 s->TxConfig = val; in rtl8139_TxConfig_write()
1707 uint32_t tc = s->TxConfig; in rtl8139_TxConfig_writeb()
1715 uint32_t ret = s->TxConfig; in rtl8139_TxConfig_read()
1727 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); in rtl8139_RxConfig_write()
1729 s->RxConfig = val; in rtl8139_RxConfig_write()
1732 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); in rtl8139_RxConfig_write()
1734 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); in rtl8139_RxConfig_write()
1739 uint32_t ret = s->RxConfig; in rtl8139_RxConfig_read()
1763 .iov_len = size - ETH_ALEN * 2 }, in rtl8139_transfer_frame()
1770 if (TxLoopBack == (s->TxConfig & TxLoopBack)) in rtl8139_transfer_frame()
1783 qemu_receive_packet(qemu_get_queue(s->nic), buf, size); in rtl8139_transfer_frame()
1792 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); in rtl8139_transfer_frame()
1794 qemu_send_packet(qemu_get_queue(s->nic), buf, size); in rtl8139_transfer_frame()
1808 if (s->TxStatus[descriptor] & TxHostOwns) in rtl8139_transmit_one()
1811 "(%08x)\n", descriptor, s->TxStatus[descriptor]); in rtl8139_transmit_one()
1818 int txsize = s->TxStatus[descriptor] & 0x1fff; in rtl8139_transmit_one()
1822 txsize, s->TxAddr[descriptor]); in rtl8139_transmit_one()
1824 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); in rtl8139_transmit_one()
1827 s->TxStatus[descriptor] |= TxHostOwns; in rtl8139_transmit_one()
1828 s->TxStatus[descriptor] |= TxStatOK; in rtl8139_transmit_one()
1836 s->IntrStatus |= TxOK; in rtl8139_transmit_one()
1842 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off…
1849 for (; len > 1; data+=2, len-=2) in ones_complement_sum()
1887 int descriptor = s->currCPlusTxDesc; in rtl8139_cplus_transmit_one()
1889 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); in rtl8139_cplus_transmit_one()
1895 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], in rtl8139_cplus_transmit_one()
1896 s->TxAddr[0], cplus_tx_ring_desc); in rtl8139_cplus_transmit_one()
1924 #define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1) in rtl8139_cplus_transmit_one()
1935 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) in rtl8139_cplus_transmit_one()
1939 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) in rtl8139_cplus_transmit_one()
1948 /* out-of-window collision flag */ in rtl8139_cplus_transmit_one()
1969 s->cplus_txbuffer_offset = 0; in rtl8139_cplus_transmit_one()
1976 if (!s->cplus_txbuffer) in rtl8139_cplus_transmit_one()
1978 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; in rtl8139_cplus_transmit_one()
1979 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); in rtl8139_cplus_transmit_one()
1980 s->cplus_txbuffer_offset = 0; in rtl8139_cplus_transmit_one()
1983 s->cplus_txbuffer_len); in rtl8139_cplus_transmit_one()
1986 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) in rtl8139_cplus_transmit_one()
1989 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; in rtl8139_cplus_transmit_one()
1998 s->cplus_txbuffer_offset); in rtl8139_cplus_transmit_one()
2001 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); in rtl8139_cplus_transmit_one()
2002 s->cplus_txbuffer_offset += txsize; in rtl8139_cplus_transmit_one()
2007 s->currCPlusTxDesc = 0; in rtl8139_cplus_transmit_one()
2011 ++s->currCPlusTxDesc; in rtl8139_cplus_transmit_one()
2012 if (s->currCPlusTxDesc >= 64) in rtl8139_cplus_transmit_one()
2013 s->currCPlusTxDesc = 0; in rtl8139_cplus_transmit_one()
2016 /* Build the Tx Status Descriptor */ in rtl8139_cplus_transmit_one()
2044 uint8_t *saved_buffer = s->cplus_txbuffer; in rtl8139_cplus_transmit_one()
2045 int saved_size = s->cplus_txbuffer_offset; in rtl8139_cplus_transmit_one()
2046 int saved_buffer_len = s->cplus_txbuffer_len; in rtl8139_cplus_transmit_one()
2052 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", in rtl8139_cplus_transmit_one()
2064 s->cplus_txbuffer = NULL; in rtl8139_cplus_transmit_one()
2065 s->cplus_txbuffer_offset = 0; in rtl8139_cplus_transmit_one()
2066 s->cplus_txbuffer_len = 0; in rtl8139_cplus_transmit_one()
2094 /* Note on memory alignment: eth_payload_data is 16-bit aligned in rtl8139_cplus_transmit_one()
2096 * even. 32-bit accesses must use ldl/stl wrappers to avoid in rtl8139_cplus_transmit_one()
2100 eth_payload_len = saved_size - ETH_HLEN; in rtl8139_cplus_transmit_one()
2116 ip_protocol = ip->ip_p; in rtl8139_cplus_transmit_one()
2118 ip_data_len = be16_to_cpu(ip->ip_len); in rtl8139_cplus_transmit_one()
2122 ip_data_len -= hlen; in rtl8139_cplus_transmit_one()
2128 ip->ip_sum = 0; in rtl8139_cplus_transmit_one()
2129 ip->ip_sum = ip_checksum(ip, hlen); in rtl8139_cplus_transmit_one()
2131 hlen, ip->ip_sum); in rtl8139_cplus_transmit_one()
2149 ip_data_len, saved_size - ETH_HLEN, large_send_mss); in rtl8139_cplus_transmit_one()
2160 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; in rtl8139_cplus_transmit_one()
2161 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; in rtl8139_cplus_transmit_one()
2173 int tcp_data_len = ip_data_len - tcp_hlen; in rtl8139_cplus_transmit_one()
2191 chunk_size = tcp_data_len - tcp_send_offset; in rtl8139_cplus_transmit_one()
2195 ldl_be_p(&p_tcp_hdr->th_seq)); in rtl8139_cplus_transmit_one()
2218 p_tcpip_hdr->zeros = 0; in rtl8139_cplus_transmit_one()
2219 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; in rtl8139_cplus_transmit_one()
2220 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); in rtl8139_cplus_transmit_one()
2222 p_tcp_hdr->th_sum = 0; in rtl8139_cplus_transmit_one()
2228 p_tcp_hdr->th_sum = tcp_checksum; in rtl8139_cplus_transmit_one()
2234 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); in rtl8139_cplus_transmit_one()
2237 … ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id)); in rtl8139_cplus_transmit_one()
2239 ip->ip_sum = 0; in rtl8139_cplus_transmit_one()
2240 ip->ip_sum = ip_checksum(eth_payload_data, hlen); in rtl8139_cplus_transmit_one()
2242 "checksum=%04x\n", hlen, ip->ip_sum); in rtl8139_cplus_transmit_one()
2251 stl_be_p(&p_tcp_hdr->th_seq, in rtl8139_cplus_transmit_one()
2252 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); in rtl8139_cplus_transmit_one()
2266 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; in rtl8139_cplus_transmit_one()
2267 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; in rtl8139_cplus_transmit_one()
2279 p_tcpip_hdr->zeros = 0; in rtl8139_cplus_transmit_one()
2280 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; in rtl8139_cplus_transmit_one()
2281 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); in rtl8139_cplus_transmit_one()
2285 p_tcp_hdr->th_sum = 0; in rtl8139_cplus_transmit_one()
2291 p_tcp_hdr->th_sum = tcp_checksum; in rtl8139_cplus_transmit_one()
2299 p_udpip_hdr->zeros = 0; in rtl8139_cplus_transmit_one()
2300 p_udpip_hdr->ip_proto = IP_PROTO_UDP; in rtl8139_cplus_transmit_one()
2301 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); in rtl8139_cplus_transmit_one()
2305 p_udp_hdr->uh_sum = 0; in rtl8139_cplus_transmit_one()
2311 p_udp_hdr->uh_sum = udp_checksum; in rtl8139_cplus_transmit_one()
2321 ++s->tally_counters.TxOk; in rtl8139_cplus_transmit_one()
2329 if (!s->cplus_txbuffer) in rtl8139_cplus_transmit_one()
2331 s->cplus_txbuffer = saved_buffer; in rtl8139_cplus_transmit_one()
2332 s->cplus_txbuffer_len = saved_buffer_len; in rtl8139_cplus_transmit_one()
2333 s->cplus_txbuffer_offset = 0; in rtl8139_cplus_transmit_one()
2361 s->currCPlusTxDesc); in rtl8139_cplus_transmit()
2366 s->IntrStatus |= TxOK; in rtl8139_cplus_transmit()
2373 int descriptor = s->currTxDesc, txcount = 0; in rtl8139_transmit()
2378 ++s->currTxDesc; in rtl8139_transmit()
2379 s->currTxDesc %= 4; in rtl8139_transmit()
2387 s->currTxDesc); in rtl8139_transmit()
2398 if (s->cplus_enabled) in rtl8139_TxStatus_write()
2404 s->TxStatus[descriptor] = val; in rtl8139_TxStatus_write()
2408 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); in rtl8139_TxStatus_write()
2414 s->TxStatus[0] &= ~0x8; in rtl8139_TxStatus_write()
2425 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); in rtl8139_TxStatus_write()
2427 s->TxStatus[descriptor] = val; in rtl8139_TxStatus_write()
2437 uint32_t reg = (addr - base) / 4; in rtl8139_TxStatus_TxAddr_read()
2441 if (addr & (size - 1)) { in rtl8139_TxStatus_TxAddr_read()
2451 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); in rtl8139_TxStatus_TxAddr_read()
2469 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) in rtl8139_TSAD_read()
2470 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) in rtl8139_TSAD_read()
2471 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) in rtl8139_TSAD_read()
2472 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) in rtl8139_TSAD_read()
2474 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) in rtl8139_TSAD_read()
2475 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) in rtl8139_TSAD_read()
2476 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) in rtl8139_TSAD_read()
2477 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) in rtl8139_TSAD_read()
2479 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) in rtl8139_TSAD_read()
2480 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) in rtl8139_TSAD_read()
2481 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) in rtl8139_TSAD_read()
2482 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) in rtl8139_TSAD_read()
2484 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) in rtl8139_TSAD_read()
2485 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) in rtl8139_TSAD_read()
2486 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) in rtl8139_TSAD_read()
2487 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; in rtl8139_TSAD_read()
2497 uint16_t ret = s->CSCR; in rtl8139_CSCR_read()
2508 s->TxAddr[txAddrOffset/4] = val; in rtl8139_TxAddr_write()
2513 uint32_t ret = s->TxAddr[txAddrOffset/4]; in rtl8139_TxAddr_read()
2525 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); in rtl8139_RxBufPtr_write()
2528 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in rtl8139_RxBufPtr_write()
2531 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); in rtl8139_RxBufPtr_write()
2537 uint32_t ret = s->RxBufPtr - 0x10; in rtl8139_RxBufPtr_read()
2547 uint32_t ret = s->RxBufAddr; in rtl8139_RxBufAddr_read()
2558 s->RxBuf = val; in rtl8139_RxBuf_write()
2565 uint32_t ret = s->RxBuf; in rtl8139_RxBuf_read()
2577 val = SET_MASKED(val, 0x1e00, s->IntrMask); in rtl8139_IntrMask_write()
2579 s->IntrMask = val; in rtl8139_IntrMask_write()
2587 uint32_t ret = s->IntrMask; in rtl8139_IntrMask_read()
2605 uint16_t newStatus = s->IntrStatus & ~val; in rtl8139_IntrStatus_write()
2608 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); in rtl8139_IntrStatus_write()
2611 s->IntrStatus = 0; in rtl8139_IntrStatus_write()
2614 s->IntrStatus = newStatus; in rtl8139_IntrStatus_write()
2623 uint32_t ret = s->IntrStatus; in rtl8139_IntrStatus_read()
2630 s->IntrStatus = 0; in rtl8139_IntrStatus_read()
2644 val = SET_MASKED(val, 0xf000, s->MultiIntr); in rtl8139_MultiIntr_write()
2646 s->MultiIntr = val; in rtl8139_MultiIntr_write()
2651 uint32_t ret = s->MultiIntr; in rtl8139_MultiIntr_read()
2665 s->phys[addr - MAC0] = val; in rtl8139_io_writeb()
2668 s->phys[addr - MAC0] = val; in rtl8139_io_writeb()
2669 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); in rtl8139_io_writeb()
2675 s->mult[addr - MAR0] = val; in rtl8139_io_writeb()
2683 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ in rtl8139_io_writeb()
2711 s->clock_enabled = 1; in rtl8139_io_writeb()
2715 s->clock_enabled = 0; in rtl8139_io_writeb()
2721 s->TxThresh = val; in rtl8139_io_writeb()
2781 s->NWayAdvert = val; in rtl8139_io_writew()
2788 s->NWayExpansion = val; in rtl8139_io_writew()
2822 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { in rtl8139_set_next_tctr_time()
2823 s->TCTR_base += ns_per_period; in rtl8139_set_next_tctr_time()
2826 if (!s->TimerInt) { in rtl8139_set_next_tctr_time()
2827 timer_del(s->timer); in rtl8139_set_next_tctr_time()
2829 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; in rtl8139_set_next_tctr_time()
2830 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { in rtl8139_set_next_tctr_time()
2833 timer_mod(s->timer, s->TCTR_base + delta); in rtl8139_set_next_tctr_time()
2845 s->RxMissed = 0; in rtl8139_io_writel()
2856 case TxStatus0 ... TxStatus0+4*4-1: in rtl8139_io_writel()
2857 rtl8139_TxStatus_write(s, addr-TxStatus0, val); in rtl8139_io_writel()
2860 case TxAddr0 ... TxAddr0+4*4-1: in rtl8139_io_writel()
2861 rtl8139_TxAddr_write(s, addr-TxAddr0, val); in rtl8139_io_writel()
2870 s->RxRingAddrLO = val; in rtl8139_io_writel()
2875 s->RxRingAddrHI = val; in rtl8139_io_writel()
2880 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in rtl8139_io_writel()
2886 if (s->TimerInt != val) { in rtl8139_io_writel()
2887 s->TimerInt = val; in rtl8139_io_writel()
2911 ret = s->phys[addr - MAC0]; in rtl8139_io_readb()
2917 ret = s->mult[addr - MAR0]; in rtl8139_io_readb()
2919 case TxStatus0 ... TxStatus0+4*4-1: in rtl8139_io_readb()
2920 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, in rtl8139_io_readb()
2947 ret = 0xd0 | (~s->BasicModeStatus & 0x04); in rtl8139_io_readb()
2952 ret = s->clock_enabled; in rtl8139_io_readb()
2962 ret = s->TxThresh; in rtl8139_io_readb()
2967 ret = s->TxConfig >> 24; in rtl8139_io_readb()
2987 case TxAddr0 ... TxAddr0+4*4-1: in rtl8139_io_readw()
2988 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); in rtl8139_io_readw()
3017 ret = s->NWayAdvert; in rtl8139_io_readw()
3021 ret = s->NWayLPAR; in rtl8139_io_readw()
3025 ret = s->NWayExpansion; in rtl8139_io_readw()
3066 ret = s->RxMissed; in rtl8139_io_readl()
3079 case TxStatus0 ... TxStatus0+4*4-1: in rtl8139_io_readl()
3080 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, in rtl8139_io_readl()
3084 case TxAddr0 ... TxAddr0+4*4-1: in rtl8139_io_readl()
3085 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); in rtl8139_io_readl()
3093 ret = s->RxRingAddrLO; in rtl8139_io_readl()
3098 ret = s->RxRingAddrHI; in rtl8139_io_readl()
3103 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / in rtl8139_io_readl()
3109 ret = s->TimerInt; in rtl8139_io_readl()
3135 s->cplus_enabled = s->CpCmd != 0; in rtl8139_post_load()
3140 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; in rtl8139_post_load()
3166 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; in rtl8139_pre_save()
3167 s->rtl8139_mmio_io_addr_dummy = 0; in rtl8139_pre_save()
3299 return -1; in rtl8139_ioport_read()
3316 if (!s->clock_enabled) in rtl8139_timer()
3322 s->IntrStatus |= PCSTimeout; in rtl8139_timer()
3331 g_free(s->cplus_txbuffer); in pci_rtl8139_uninit()
3332 s->cplus_txbuffer = NULL; in pci_rtl8139_uninit()
3333 timer_free(s->timer); in pci_rtl8139_uninit()
3334 qemu_del_nic(s->nic); in pci_rtl8139_uninit()
3341 if (nc->link_down) { in rtl8139_set_link_status()
3342 s->BasicModeStatus &= ~0x04; in rtl8139_set_link_status()
3344 s->BasicModeStatus |= 0x04; in rtl8139_set_link_status()
3347 s->IntrStatus |= RxUnderrun; in rtl8139_set_link_status()
3365 pci_conf = dev->config; in pci_rtl8139_realize()
3371 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, in pci_rtl8139_realize()
3373 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, in pci_rtl8139_realize()
3376 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); in pci_rtl8139_realize()
3377 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); in pci_rtl8139_realize()
3379 qemu_macaddr_default_if_unset(&s->conf.macaddr); in pci_rtl8139_realize()
3382 s->eeprom.contents[0] = 0x8129; in pci_rtl8139_realize()
3385 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; in pci_rtl8139_realize()
3386 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; in pci_rtl8139_realize()
3388 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; in pci_rtl8139_realize()
3389 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; in pci_rtl8139_realize()
3390 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; in pci_rtl8139_realize()
3392 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, in pci_rtl8139_realize()
3393 object_get_typename(OBJECT(dev)), d->id, in pci_rtl8139_realize()
3394 &d->mem_reentrancy_guard, s); in pci_rtl8139_realize()
3395 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in pci_rtl8139_realize()
3397 s->cplus_txbuffer = NULL; in pci_rtl8139_realize()
3398 s->cplus_txbuffer_len = 0; in pci_rtl8139_realize()
3399 s->cplus_txbuffer_offset = 0; in pci_rtl8139_realize()
3401 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); in pci_rtl8139_realize()
3408 device_add_bootindex_property(obj, &s->conf.bootindex, in rtl8139_instance_init()
3409 "bootindex", "/ethernet-phy@0", in rtl8139_instance_init()
3423 k->realize = pci_rtl8139_realize; in rtl8139_class_init()
3424 k->exit = pci_rtl8139_uninit; in rtl8139_class_init()
3425 k->romfile = "efi-rtl8139.rom"; in rtl8139_class_init()
3426 k->vendor_id = PCI_VENDOR_ID_REALTEK; in rtl8139_class_init()
3427 k->device_id = PCI_DEVICE_ID_REALTEK_8139; in rtl8139_class_init()
3428 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ in rtl8139_class_init()
3429 k->class_id = PCI_CLASS_NETWORK_ETHERNET; in rtl8139_class_init()
3431 dc->vmsd = &vmstate_rtl8139; in rtl8139_class_init()
3433 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); in rtl8139_class_init()