Lines Matching +full:0 +full:x00000053
211 VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
251 s->phy_status &= ~0x0024; in imx_phy_update_link()
255 s->phy_status |= 0x0024; in imx_phy_update_link()
271 s->phy_status = 0x7809; in imx_phy_reset()
272 s->phy_control = 0x3000; in imx_phy_reset()
273 s->phy_advertise = 0x01e1; in imx_phy_reset()
274 s->phy_int_mask = 0; in imx_phy_reset()
275 s->phy_int = 0; in imx_phy_reset()
285 return 0xffff; in imx_phy_read()
293 return 0xffff; in imx_phy_read()
300 case 0: /* Basic Control */ in imx_phy_read()
307 val = 0x0007; in imx_phy_read()
310 val = 0xc0d1; in imx_phy_read()
316 val = 0x0f71; in imx_phy_read()
323 s->phy_int = 0; in imx_phy_read()
335 val = 0; in imx_phy_read()
340 val = 0; in imx_phy_read()
371 case 0: /* Basic Control */ in imx_phy_write()
372 if (val & 0x8000) { in imx_phy_write()
375 s->phy_control = val & 0x7980; in imx_phy_write()
377 if (val & 0x1000) { in imx_phy_write()
378 s->phy_status |= 0x0020; in imx_phy_write()
383 s->phy_advertise = (val & 0x2d7f) | 0x80; in imx_phy_write()
386 s->phy_int_mask = val & 0xff; in imx_phy_write()
463 qemu_set_irq(s->irq[1], 0); in imx_eth_update()
467 qemu_set_irq(s->irq[0], 1); in imx_eth_update()
469 qemu_set_irq(s->irq[0], 0); in imx_eth_update()
475 int frame_size = 0, descnt = 0; in imx_fec_do_tx()
477 uint32_t addr = s->tx_descriptor[0]; in imx_fec_do_tx()
484 if ((bd.flags & ENET_BD_R) == 0) { in imx_fec_do_tx()
504 frame_size = 0; in imx_fec_do_tx()
512 if ((bd.flags & ENET_BD_W) != 0) { in imx_fec_do_tx()
519 s->tx_descriptor[0] = addr; in imx_fec_do_tx()
526 int frame_size = 0, descnt = 0; in imx_enet_do_tx()
534 ring = 0; in imx_enet_do_tx()
566 if ((bd.flags & ENET_BD_R) == 0) { in imx_enet_do_tx()
583 int csum = 0; in imx_enet_do_tx()
600 frame_size = 0; in imx_enet_do_tx()
614 if ((bd.flags & ENET_BD_W) != 0) { in imx_enet_do_tx()
641 s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; in imx_eth_enable_rx()
655 memset(s->regs, 0, sizeof(s->regs)); in imx_eth_reset()
656 s->regs[ENET_ECR] = 0xf0000000; in imx_eth_reset()
657 s->regs[ENET_MIBC] = 0xc0000000; in imx_eth_reset()
658 s->regs[ENET_RCR] = 0x05ee0001; in imx_eth_reset()
659 s->regs[ENET_OPD] = 0x00010000; in imx_eth_reset()
661 s->regs[ENET_PALR] = (s->conf.macaddr.a[0] << 24) in imx_eth_reset()
667 | 0x8808; in imx_eth_reset()
670 s->regs[ENET_FRBR] = 0x00000600; in imx_eth_reset()
671 s->regs[ENET_FRSR] = 0x00000500; in imx_eth_reset()
672 s->regs[ENET_MIIGSK_ENR] = 0x00000006; in imx_eth_reset()
674 s->regs[ENET_RAEM] = 0x00000004; in imx_eth_reset()
675 s->regs[ENET_RAFL] = 0x00000004; in imx_eth_reset()
676 s->regs[ENET_TAEM] = 0x00000004; in imx_eth_reset()
677 s->regs[ENET_TAFL] = 0x00000008; in imx_eth_reset()
678 s->regs[ENET_TIPG] = 0x0000000c; in imx_eth_reset()
679 s->regs[ENET_FTRL] = 0x000007ff; in imx_eth_reset()
680 s->regs[ENET_ATPER] = 0x3b9aca00; in imx_eth_reset()
683 s->rx_descriptor = 0; in imx_eth_reset()
684 memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); in imx_eth_reset()
692 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" in imx_default_read()
694 return 0; in imx_default_read()
748 uint32_t value = 0; in imx_eth_read()
792 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" in imx_default_write()
806 s->regs[index] = (value & 0x000003fc) | 0x00000400; in imx_fec_write()
809 s->regs[index] = value & 0x00000053; in imx_fec_write()
812 s->regs[index] = (value & 0x00000002) ? 0x00000006 : 0; in imx_fec_write()
830 s->regs[index] = value & 0x000001ff; in imx_enet_write()
833 s->regs[index] = value & 0x0000001f; in imx_enet_write()
836 s->regs[index] = value & 0x00003fff; in imx_enet_write()
839 s->regs[index] = value & 0x00000019; in imx_enet_write()
842 s->regs[index] = value & 0x000000C7; in imx_enet_write()
845 s->regs[index] = value & 0x00002a9d; in imx_enet_write()
858 s->regs[index] = value & 0x7fffffff; in imx_enet_write()
861 s->regs[index] = value & 0x00007f7f; in imx_enet_write()
865 s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */ in imx_enet_write()
871 s->regs[index] &= ~(value & 0x00000080); /* W1C bits */ in imx_enet_write()
872 s->regs[index] &= ~0x0000007d; /* writable fields */ in imx_enet_write()
873 s->regs[index] |= (value & 0x0000007d); in imx_enet_write()
909 s->regs[index] = 0; in imx_eth_write()
926 s->regs[index] = 0; in imx_eth_write()
933 if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) { in imx_eth_write()
934 s->regs[ENET_RDAR] = 0; in imx_eth_write()
936 s->regs[ENET_TDAR] = 0; in imx_eth_write()
937 s->regs[ENET_TDAR1] = 0; in imx_eth_write()
938 s->regs[ENET_TDAR2] = 0; in imx_eth_write()
939 s->tx_descriptor[0] = s->regs[ENET_TDSR]; in imx_eth_write()
948 s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16, in imx_eth_write()
954 imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); in imx_eth_write()
960 s->regs[index] = value & 0xfe; in imx_eth_write()
964 s->regs[index] = (value & 0x80000000) ? 0xc0000000 : 0; in imx_eth_write()
967 s->regs[index] = value & 0x07ff003f; in imx_eth_write()
979 s->conf.macaddr.a[0] = value >> 24; in imx_eth_write()
985 s->regs[index] = (value | 0x0000ffff) & 0xffff8808; in imx_eth_write()
990 s->regs[index] = (value & 0x0000ffff) | 0x00010000; in imx_eth_write()
1000 s->regs[index] = value & 0x3; in imx_eth_write()
1002 s->regs[index] = value & 0x13f; in imx_eth_write()
1019 s->tx_descriptor[0] = s->regs[index]; in imx_eth_write()
1044 s->regs[index] = value & 0x00003ff0; in imx_eth_write()
1070 uint32_t flags = 0; in imx_fec_receive()
1083 return 0; in imx_fec_receive()
1086 crc = cpu_to_be32(crc32(~0, buf, size)); in imx_fec_receive()
1103 while (size > 0) { in imx_fec_receive()
1105 if ((bd.flags & ENET_BD_E) == 0) { in imx_fec_receive()
1136 if (size == 0) { in imx_fec_receive()
1148 if ((bd.flags & ENET_BD_W) != 0) { in imx_fec_receive()
1165 uint32_t flags = 0; in imx_enet_receive()
1179 return 0; in imx_enet_receive()
1182 crc = cpu_to_be32(crc32(~0, buf, size)); in imx_enet_receive()
1203 while (size > 0) { in imx_enet_receive()
1205 if ((bd.flags & ENET_BD_E) == 0) { in imx_enet_receive()
1233 const uint8_t zeros[2] = { 0 }; in imx_enet_receive()
1254 if (size == 0) { in imx_enet_receive()
1272 if ((bd.flags & ENET_BD_W) != 0) { in imx_enet_receive()
1329 sysbus_init_irq(sbd, &s->irq[0]); in imx_eth_realize()
1344 DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),