Lines Matching refs:mac_reg
90 uint32_t mac_reg[0x8000]; member
161 e1000x_update_regs_on_link_up(s->mac_reg, s->phy_reg); in DECLARE_OBJ_CHECKERS()
170 e1000x_update_regs_on_autoneg_done(s->mac_reg, s->phy_reg); in e1000_autoneg_done()
196 e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); in set_phy_ctrl()
281 s->mac_reg[ICR] = val; in set_interrupt_cause()
291 s->mac_reg[ICS] = val; in set_interrupt_cause()
293 pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); in set_interrupt_cause()
316 mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4); in set_interrupt_cause()
318 if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) { in set_interrupt_cause()
319 mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4); in set_interrupt_cause()
321 mit_update_delay(&mit_delay, s->mac_reg[ITR]); in set_interrupt_cause()
348 set_interrupt_cause(s, 0, s->mac_reg[ICR]); in e1000_mit_timer()
354 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], in set_ics()
355 s->mac_reg[IMS]); in set_ics()
356 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); in set_ics()
391 memset(d->mac_reg, 0, sizeof d->mac_reg); in e1000_reset_hold()
392 memcpy(d->mac_reg, mac_reg_init, sizeof mac_reg_init); in e1000_reset_hold()
397 e1000x_update_regs_on_link_down(d->mac_reg, d->phy_reg); in e1000_reset_hold()
400 e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr); in e1000_reset_hold()
403 d->mac_reg[VET] = ETH_P_VLAN; in e1000_reset_hold()
411 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; in set_ctrl()
425 s->mac_reg[RCTL] = val; in set_rx_control()
428 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], in set_rx_control()
429 s->mac_reg[RCTL]); in set_rx_control()
441 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; in set_mdic()
462 s->mac_reg[MDIC] = val | E1000_MDIC_READY; in set_mdic()
522 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; in flash_eerd_read()
524 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) in flash_eerd_read()
525 return (s->mac_reg[EERD]); in flash_eerd_read()
551 e1000x_inc_reg_if_not_full(s->mac_reg, BPTC); in inc_tx_bcast_or_mcast_count()
553 e1000x_inc_reg_if_not_full(s->mac_reg, MPTC); in inc_tx_bcast_or_mcast_count()
570 e1000x_increase_size_stats(s->mac_reg, PTCregs, size + 4); in e1000_send_packet()
601 e1000x_inc_reg_if_not_full(s->mac_reg, TSCTC); in xmit_seg()
633 e1000x_inc_reg_if_not_full(s->mac_reg, TPT); in xmit_seg()
634 e1000x_grow_8reg_if_not_full(s->mac_reg, TOTL, s->tx.size + 4); in xmit_seg()
635 e1000x_inc_reg_if_not_full(s->mac_reg, GPTC); in xmit_seg()
636 e1000x_grow_8reg_if_not_full(s->mac_reg, GOTCL, s->tx.size + 4); in xmit_seg()
673 if (e1000x_vlan_enabled(s->mac_reg) && in process_tx_desc()
678 le16_to_cpu(s->mac_reg[VET])); in process_tx_desc()
747 uint64_t bah = s->mac_reg[TDBAH]; in tx_desc_base()
748 uint64_t bal = s->mac_reg[TDBAL] & ~0xf; in tx_desc_base()
759 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; in start_xmit()
761 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { in start_xmit()
771 while (s->mac_reg[TDH] != s->mac_reg[TDT]) { in start_xmit()
773 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; in start_xmit()
776 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], in start_xmit()
783 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) in start_xmit()
784 s->mac_reg[TDH] = 0; in start_xmit()
790 if (s->mac_reg[TDH] == tdh_start || in start_xmit()
791 tdh_start >= s->mac_reg[TDLEN] / sizeof(desc)) { in start_xmit()
793 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); in start_xmit()
804 return (!e1000x_is_vlan_packet(buf, s->mac_reg[VET]) || in receive_filter()
805 e1000x_rx_vlan_filter(s->mac_reg, PKT_GET_VLAN_HDR(buf))) && in receive_filter()
806 e1000x_rx_group_filter(s->mac_reg, buf); in receive_filter()
813 uint32_t old_status = s->mac_reg[STATUS]; in e1000_set_link_status()
816 e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg); in e1000_set_link_status()
820 e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); in e1000_set_link_status()
826 if (s->mac_reg[STATUS] != old_status) in e1000_set_link_status()
835 return s->mac_reg[RDH] != s->mac_reg[RDT]; in e1000_has_rxbufs()
837 if (s->mac_reg[RDH] < s->mac_reg[RDT]) { in e1000_has_rxbufs()
838 bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; in e1000_has_rxbufs()
839 } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) { in e1000_has_rxbufs()
840 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + in e1000_has_rxbufs()
841 s->mac_reg[RDT] - s->mac_reg[RDH]; in e1000_has_rxbufs()
853 return e1000x_rx_ready(&s->parent_obj, s->mac_reg) && in e1000_can_receive()
859 uint64_t bah = s->mac_reg[RDBAH]; in rx_desc_base()
860 uint64_t bal = s->mac_reg[RDBAL] & ~0xf; in rx_desc_base()
868 trace_e1000_receiver_overrun(size, s->mac_reg[RDH], s->mac_reg[RDT]); in e1000_receiver_overrun()
869 e1000x_inc_reg_if_not_full(s->mac_reg, RNBC); in e1000_receiver_overrun()
870 e1000x_inc_reg_if_not_full(s->mac_reg, MPC); in e1000_receiver_overrun()
894 if (!e1000x_hw_rx_enabled(s->mac_reg)) { in e1000_receive_iov()
909 if (e1000x_is_oversized(s->mac_reg, size)) { in e1000_receive_iov()
917 if (e1000x_vlan_enabled(s->mac_reg) && in e1000_receive_iov()
918 e1000x_is_vlan_packet(filter_buf, le16_to_cpu(s->mac_reg[VET]))) { in e1000_receive_iov()
935 rdh_start = s->mac_reg[RDH]; in e1000_receive_iov()
937 total_size = size + e1000x_fcs_len(s->mac_reg); in e1000_receive_iov()
947 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH]; in e1000_receive_iov()
988 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) in e1000_receive_iov()
989 s->mac_reg[RDH] = 0; in e1000_receive_iov()
991 if (s->mac_reg[RDH] == rdh_start || in e1000_receive_iov()
992 rdh_start >= s->mac_reg[RDLEN] / sizeof(desc)) { in e1000_receive_iov()
994 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); in e1000_receive_iov()
1000 e1000x_update_rx_total_stats(s->mac_reg, pkt_type, size, total_size); in e1000_receive_iov()
1003 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) in e1000_receive_iov()
1004 rdt += s->mac_reg[RDLEN] / sizeof(desc); in e1000_receive_iov()
1005 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> in e1000_receive_iov()
1028 return s->mac_reg[index]; in mac_readreg()
1034 uint32_t ret = s->mac_reg[ICR]; in mac_icr_read()
1044 uint32_t ret = s->mac_reg[index]; in mac_read_clr4()
1046 s->mac_reg[index] = 0; in mac_read_clr4()
1053 uint32_t ret = s->mac_reg[index]; in mac_read_clr8()
1055 s->mac_reg[index] = 0; in mac_read_clr8()
1056 s->mac_reg[index-1] = 0; in mac_read_clr8()
1065 s->mac_reg[index] = val; in mac_writereg()
1068 macaddr[0] = cpu_to_le32(s->mac_reg[RA]); in mac_writereg()
1069 macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]); in mac_writereg()
1077 s->mac_reg[index] = val & 0xffff; in set_rdt()
1087 s->mac_reg[index] = val & (BIT(num) - 1); \
1098 s->mac_reg[index] = val & 0xfff80; in set_dlen()
1104 s->mac_reg[index] = val; in set_tctl()
1105 s->mac_reg[TDT] &= 0xffff; in set_tctl()
1113 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); in set_icr()
1119 s->mac_reg[IMS] &= ~val; in set_imc()
1126 s->mac_reg[IMS] |= val; in set_ims()
1396 nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; in e1000_post_load()
1441 VMSTATE_UINT32(mac_reg[RDTR], E1000State),
1442 VMSTATE_UINT32(mac_reg[RADV], E1000State),
1443 VMSTATE_UINT32(mac_reg[TADV], E1000State),
1444 VMSTATE_UINT32(mac_reg[ITR], E1000State),
1456 VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
1518 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1519 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1520 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1521 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1522 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1523 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1524 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1525 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1526 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1527 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1528 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1529 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1530 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1531 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1532 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1533 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1534 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1535 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1536 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1537 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1538 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1539 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1540 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1541 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1542 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1543 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1544 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1545 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1546 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1547 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1548 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1549 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1550 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1551 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1552 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1553 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1554 VMSTATE_UINT32(mac_reg[VET], E1000State),
1555 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1556 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, E1000_MC_TBL_SIZE),
1557 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA,