62     } while (0)
64 #define DBGOUT(what, fmt, ...) do {} while (0)
67 #define IOPORT_SIZE       0x40
68 #define PNPMMIO_SIZE      0x20000
90     uint32_t mac_reg[0x8000];
91     uint16_t phy_reg[0x20];
101         unsigned char data[0x10000];
129 /* Compatibility flags for migration to/from qemu 1.3.0 and older */
185     /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */  in set_phy_ctrl()
186     s->phy_reg[MII_BMCR] = val & ~(0x3f |  in set_phy_ctrl()
207 static const char phy_regcap[0x20] = {
234     [MII_PHYID1] = 0x141,
246     [M88E1000_PHY_SPEC_CTRL] = 0x360,
247     [M88E1000_PHY_SPEC_STATUS] = 0xac00,
248     [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60,
252     [PBA]     = 0x00100030,
253     [LEDCTL]  = 0x602,
256     [STATUS]  = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
265 /* Helper function, *curr == 0 means the value is not set */
269     if (value && (*curr == 0 || value < *curr)) {  in mit_update_delay()
310          * RDTR!=0), TADV and ITR.  in set_interrupt_cause()
313         mit_delay = 0;  in set_interrupt_cause()
334         s->mit_ide = 0;  in set_interrupt_cause()
337     s->mit_irq_level = (pending_ints != 0);  in set_interrupt_cause()
346     s->mit_timer_on = 0;  in e1000_mit_timer()
348     set_interrupt_cause(s, 0, s->mac_reg[ICR]);  in e1000_mit_timer()
356     set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);  in set_ics()
365         set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */  in e1000_autoneg_timer()
385     d->mit_timer_on = 0;  in e1000_reset_hold()
386     d->mit_irq_level = 0;  in e1000_reset_hold()
387     d->mit_ide = 0;  in e1000_reset_hold()
388     memset(d->phy_reg, 0, sizeof d->phy_reg);  in e1000_reset_hold()
391     memset(d->mac_reg, 0, sizeof d->mac_reg);  in e1000_reset_hold()
394     memset(&d->tx, 0, sizeof d->tx);  in e1000_reset_hold()
428     DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],  in set_rx_control()
443         DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);  in set_mdic()
450         DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);  in set_mdic()
465         set_ics(s, 0, E1000_ICR_MDAC);  in set_mdic()
477         ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>  in get_eecd()
478           ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)  in get_eecd()
494         s->eecd_state.val_in = 0;  in set_eecd()
495         s->eecd_state.bitnum_in = 0;  in set_eecd()
496         s->eecd_state.bitnum_out = 0;  in set_eecd()
497         s->eecd_state.reading = 0;  in set_eecd()
510         s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;  in set_eecd()
524     if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)  in flash_eerd_read()
612             phsum = (phsum >> 16) + (phsum & 0xffff);  in xmit_seg()
645     unsigned int split_size = txd_lower & 0xffff, bytes, sz;  in process_tx_desc()
646     unsigned int msh = 0xfffff;  in process_tx_desc()
656             tp->tso_frames = 0;  in process_tx_desc()
659             s->use_tso_for_migration = 0;  in process_tx_desc()
664         if (tp->size == 0) {  in process_tx_desc()
667         tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;  in process_tx_desc()
670         tp->cptse = 0;  in process_tx_desc()
722     tp->tso_frames = 0;  in process_tx_desc()
723     tp->sum_needed = 0;  in process_tx_desc()
724     tp->vlan_needed = 0;  in process_tx_desc()
725     tp->size = 0;  in process_tx_desc()
726     tp->cptse = 0;  in process_tx_desc()
736         return 0;  in txdesc_writeback()
748     uint64_t bal = s->mac_reg[TDBAL] & ~0xf;  in tx_desc_base()
784             s->mac_reg[TDH] = 0;  in start_xmit()
798     set_ics(s, 0, cause);  in start_xmit()
827         set_ics(s, 0, E1000_ICR_LSC);  in e1000_set_link_status()
860     uint64_t bal = s->mac_reg[RDBAL] & ~0xf;  in rx_desc_base()
871     set_ics(s, 0, E1000_ICS_RXO);  in e1000_receiver_overrun()
883     uint16_t vlan_special = 0;  in e1000_receive_iov()
884     uint8_t vlan_status = 0;  in e1000_receive_iov()
888     size_t iov_ofs = 0;  in e1000_receive_iov()
899         return 0;  in e1000_receive_iov()
904         iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN);  in e1000_receive_iov()
936     desc_offset = 0;  in e1000_receive_iov()
967                         iov_ofs = 0;  in e1000_receive_iov()
989             s->mac_reg[RDH] = 0;  in e1000_receive_iov()
1009     set_ics(s, 0, n);  in e1000_receive_iov()
1037     set_interrupt_cause(s, 0, 0);  in mac_icr_read()
1046     s->mac_reg[index] = 0;  in mac_read_clr4()
1055     s->mac_reg[index] = 0;  in mac_read_clr8()
1056     s->mac_reg[index-1] = 0;  in mac_read_clr8()
1068         macaddr[0] = cpu_to_le32(s->mac_reg[RA]);  in mac_writereg()
1077     s->mac_reg[index] = val & 0xffff;  in set_rdt()
1098     s->mac_reg[index] = val & 0xfff80;  in set_dlen()
1105     s->mac_reg[TDT] &= 0xffff;  in set_tctl()
1113     set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);  in set_icr()
1120     set_ics(s, 0, 0);  in set_imc()
1127     set_ics(s, 0, 0);  in set_ims()
1220 static const uint8_t mac_reg_access[0x8000] = {
1268     unsigned int index = (addr & 0x1ffff) >> 2;  in e1000_mmio_write()
1274                 DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "  in e1000_mmio_write()
1279             DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n",  in e1000_mmio_write()
1283         DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n",  in e1000_mmio_write()
1286         DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",  in e1000_mmio_write()
1295     unsigned int index = (addr & 0x1ffff) >> 2;  in e1000_mmio_read()
1301                 DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "  in e1000_mmio_read()
1306             DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n",  in e1000_mmio_read()
1310         DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);  in e1000_mmio_read()
1312     return 0;  in e1000_mmio_read()
1331     return 0;  in e1000_io_read()
1381     return 0;  in e1000_pre_save()
1389     s->mit_ide = 0;  in e1000_post_load()
1396     nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;  in e1000_post_load()
1412     return 0;  in e1000_post_load()
1419     return 0;  in e1000_tx_tso_post_load()
1456         VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
1517         VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1574     0x0000, 0x0000, 0x0000, 0x0000,      0xffff, 0x0000,      0x0000, 0x0000,
1575     0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,
1576     0x0008, 0x2000, 0x7e14, 0x0048,      0x1000, 0x00d8,      0x0000, 0x2700,
1577     0x6cc9, 0x3150, 0x0722, 0x040b,      0x0984, 0x0000,      0xc000, 0x0706,
1578     0x1008, 0x0000, 0x0f04, 0x7fff,      0x4d01, 0xffff,      0xffff, 0xffff,
1579     0xffff, 0xffff, 0xffff, 0xffff,      0xffff, 0xffff,      0xffff, 0xffff,
1580     0x0100, 0x4000, 0x121c, 0xffff,      0xffff, 0xffff,      0xffff, 0xffff,
1581     0xffff, 0xffff, 0xffff, 0xffff,      0xffff, 0xffff,      0xffff, 0x0000,
1597     memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);  in e1000_mmio_setup()
1598     for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)  in e1000_mmio_setup()
1648     /* TODO: RST# value should be 0, PCI spec 6.2.4 */  in pci_e1000_realize()
1649     pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;  in pci_e1000_realize()
1655     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);  in pci_e1000_realize()
1724                                   "bootindex", "/ethernet-phy@0",  in e1000_instance_init()
1745         .revision  = 0x03,
1751         .revision  = 0x03,
1757         .revision  = 0x03,
1767     for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) {  in e1000_register_types()